171 lines
5.4 KiB
C
171 lines
5.4 KiB
C
/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_OPP_DCN20_H__
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#define __DC_OPP_DCN20_H__
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#include "dcn10/dcn10_opp.h"
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#define TO_DCN20_OPP(opp)\
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container_of(opp, struct dcn20_opp, base)
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#define OPP_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define OPP_DPG_REG_LIST(id) \
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SRI(DPG_CONTROL, DPG, id), \
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SRI(DPG_DIMENSIONS, DPG, id), \
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SRI(DPG_OFFSET_SEGMENT, DPG, id), \
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SRI(DPG_COLOUR_B_CB, DPG, id), \
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SRI(DPG_COLOUR_G_Y, DPG, id), \
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SRI(DPG_COLOUR_R_CR, DPG, id), \
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SRI(DPG_RAMP_CONTROL, DPG, id), \
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SRI(DPG_STATUS, DPG, id)
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#define OPP_REG_LIST_DCN20(id) \
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OPP_REG_LIST_DCN10(id), \
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OPP_DPG_REG_LIST(id), \
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SRI(FMT_422_CONTROL, FMT, id), \
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SRI(OPPBUF_CONTROL1, OPPBUF, id)
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#define OPP_REG_VARIABLE_LIST_DCN2_0 \
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OPP_COMMON_REG_VARIABLE_LIST; \
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uint32_t FMT_422_CONTROL; \
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uint32_t DPG_CONTROL; \
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uint32_t DPG_DIMENSIONS; \
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uint32_t DPG_OFFSET_SEGMENT; \
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uint32_t DPG_COLOUR_B_CB; \
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uint32_t DPG_COLOUR_G_Y; \
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uint32_t DPG_COLOUR_R_CR; \
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uint32_t DPG_RAMP_CONTROL; \
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uint32_t DPG_STATUS
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#define OPP_DPG_MASK_SH_LIST(mask_sh) \
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OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \
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OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \
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OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \
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OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \
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OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \
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OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \
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OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \
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OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \
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OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_X_OFFSET, mask_sh), \
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OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_SEGMENT_WIDTH, mask_sh), \
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OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \
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OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \
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OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \
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OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR1_B_CB, mask_sh), \
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OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \
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OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \
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OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_RAMP0_OFFSET, mask_sh), \
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OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \
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OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC1, mask_sh), \
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OPP_SF(DPG0_DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, mask_sh)
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#define OPP_MASK_SH_LIST_DCN20(mask_sh) \
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OPP_MASK_SH_LIST_DCN(mask_sh), \
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OPP_DPG_MASK_SH_LIST(mask_sh), \
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OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\
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OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh), \
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OPP_SF(FMT0_FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, mask_sh)
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#define OPP_DCN20_REG_FIELD_LIST(type) \
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OPP_DCN10_REG_FIELD_LIST(type); \
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type FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT; \
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type DPG_EN; \
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type DPG_MODE; \
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type DPG_DYNAMIC_RANGE; \
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type DPG_BIT_DEPTH; \
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type DPG_VRES; \
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type DPG_HRES; \
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type DPG_ACTIVE_WIDTH; \
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type DPG_ACTIVE_HEIGHT; \
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type DPG_X_OFFSET; \
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type DPG_SEGMENT_WIDTH; \
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type DPG_COLOUR0_R_CR; \
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type DPG_COLOUR1_R_CR; \
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type DPG_COLOUR0_B_CB; \
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type DPG_COLOUR1_B_CB; \
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type DPG_COLOUR0_G_Y; \
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type DPG_COLOUR1_G_Y; \
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type DPG_RAMP0_OFFSET; \
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type DPG_INC0; \
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type DPG_INC1; \
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type DPG_DOUBLE_BUFFER_PENDING
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struct dcn20_opp_registers {
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OPP_REG_VARIABLE_LIST_DCN2_0;
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};
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struct dcn20_opp_shift {
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OPP_DCN20_REG_FIELD_LIST(uint8_t);
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};
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struct dcn20_opp_mask {
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OPP_DCN20_REG_FIELD_LIST(uint32_t);
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};
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struct dcn20_opp {
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struct output_pixel_processor base;
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const struct dcn20_opp_registers *regs;
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const struct dcn20_opp_shift *opp_shift;
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const struct dcn20_opp_mask *opp_mask;
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bool is_write_to_ram_a_safe;
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};
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void dcn20_opp_construct(struct dcn20_opp *oppn20,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn20_opp_registers *regs,
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const struct dcn20_opp_shift *opp_shift,
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const struct dcn20_opp_mask *opp_mask);
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void opp2_set_disp_pattern_generator(
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struct output_pixel_processor *opp,
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enum controller_dp_test_pattern test_pattern,
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enum controller_dp_color_space color_space,
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enum dc_color_depth color_depth,
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const struct tg_color *solid_color,
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int width,
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int height,
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int offset);
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void opp2_program_dpg_dimensions(
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struct output_pixel_processor *opp,
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int width, int height);
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bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);
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void opp2_dpg_set_blank_color(
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struct output_pixel_processor *opp,
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const struct tg_color *color);
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void opp2_program_left_edge_extra_pixel (
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struct output_pixel_processor *opp,
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bool count);
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#endif
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