133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dcn20/dcn20_dccg.h"
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#include "dcn21_dccg.h"
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#define TO_DCN_DCCG(dccg)\
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container_of(dccg, struct dcn_dccg, base)
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#define REG(reg) \
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(dccg_dcn->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
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#define CTX \
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dccg_dcn->base.ctx
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#define DC_LOGGER \
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dccg->ctx->logger
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void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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if (dccg->ref_dppclk) {
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int ref_dppclk = dccg->ref_dppclk;
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int modulo = ref_dppclk / 10000;
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int phase;
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if (req_dppclk) {
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/*
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* program DPP DTO phase and modulo as below
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* phase = ceiling(dpp_pipe_clk_mhz / 10)
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* module = trunc(dpp_global_clk_mhz / 10)
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*
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* storing frequencies in registers allow dmcub fw
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* to run time lower clocks when possible for power saving
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*
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* ceiling phase and truncate modulo guarentees the divided
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* down per pipe dpp clock has high enough frequency
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*/
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phase = (req_dppclk + 9999) / 10000;
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if (phase > modulo) {
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/* phase > modulo result in screen corruption
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* ie phase = 30, mod = 29 for 4k@60 HDMI
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* in these case we don't want pipe clock to be divided
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*/
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phase = modulo;
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}
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} else {
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/*
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* set phase to 10 if dpp isn't used to
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* prevent hard hang if access dpp register
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* on unused pipe
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*
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* DTO should be on to divide down un-used
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* pipe clock for power saving
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*/
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phase = 10;
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}
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REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
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DPPCLK0_DTO_PHASE, phase,
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DPPCLK0_DTO_MODULO, modulo);
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REG_UPDATE(DPPCLK_DTO_CTRL,
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DPPCLK_DTO_ENABLE[dpp_inst], 1);
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}
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dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
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}
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static const struct dccg_funcs dccg21_funcs = {
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.update_dpp_dto = dccg21_update_dpp_dto,
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.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
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.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
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.otg_add_pixel = dccg2_otg_add_pixel,
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.otg_drop_pixel = dccg2_otg_drop_pixel,
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.dccg_init = dccg2_init
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};
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struct dccg *dccg21_create(
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struct dc_context *ctx,
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const struct dccg_registers *regs,
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const struct dccg_shift *dccg_shift,
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const struct dccg_mask *dccg_mask)
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{
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struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
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struct dccg *base;
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if (dccg_dcn == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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base = &dccg_dcn->base;
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base->ctx = ctx;
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base->funcs = &dccg21_funcs;
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dccg_dcn->regs = regs;
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dccg_dcn->dccg_shift = dccg_shift;
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dccg_dcn->dccg_mask = dccg_mask;
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return &dccg_dcn->base;
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}
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