474 lines
15 KiB
C
474 lines
15 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "reg_helper.h"
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#include "dcn30_hubbub.h"
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#define CTX \
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hubbub1->base.ctx
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#define DC_LOGGER \
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hubbub1->base.ctx->logger
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#define REG(reg)\
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hubbub1->regs->reg
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#undef FN
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#define FN(reg_name, field_name) \
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hubbub1->shifts->field_name, hubbub1->masks->field_name
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#ifdef NUM_VMID
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#undef NUM_VMID
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#endif
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#define NUM_VMID 16
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static uint32_t convert_and_clamp(
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uint32_t wm_ns,
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uint32_t refclk_mhz,
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uint32_t clamp_value)
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{
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uint32_t ret_val = 0;
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ret_val = wm_ns * refclk_mhz;
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ret_val /= 1000;
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if (ret_val > clamp_value)
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ret_val = clamp_value;
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return ret_val;
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}
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int hubbub3_init_dchub_sys_ctx(struct hubbub *hubbub,
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struct dcn_hubbub_phys_addr_config *pa_config)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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struct dcn_vmid_page_table_config phys_config;
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REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
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FB_BASE, pa_config->system_aperture.fb_base >> 24);
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REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
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FB_TOP, pa_config->system_aperture.fb_top >> 24);
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REG_SET(DCN_VM_FB_OFFSET, 0,
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FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
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REG_SET(DCN_VM_AGP_BOT, 0,
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AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
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REG_SET(DCN_VM_AGP_TOP, 0,
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AGP_TOP, pa_config->system_aperture.agp_top >> 24);
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REG_SET(DCN_VM_AGP_BASE, 0,
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AGP_BASE, pa_config->system_aperture.agp_base >> 24);
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if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
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phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
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phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
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phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
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phys_config.depth = 0;
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phys_config.block_size = 0;
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// Init VMID 0 based on PA config
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dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
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}
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return NUM_VMID;
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}
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bool hubbub3_program_watermarks(
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struct hubbub *hubbub,
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struct dcn_watermark_set *watermarks,
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unsigned int refclk_mhz,
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bool safe_to_lower)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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bool wm_pending = false;
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if (hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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if (hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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if (hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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/*
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* The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
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* If the memory controller is fully utilized and the DCHub requestors are
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* well ahead of their amortized schedule, then it is safe to prevent the next winner
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* from being committed and sent to the fabric.
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* The utilization of the memory controller is approximated by ensuring that
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* the number of outstanding requests is greater than a threshold specified
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* by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
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* the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
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*
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* TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF)
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* to turn off it for now.
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*/
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REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
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DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
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REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
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DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);
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hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
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return wm_pending;
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}
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bool hubbub3_dcc_support_swizzle(
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enum swizzle_mode_values swizzle,
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unsigned int bytes_per_element,
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enum segment_order *segment_order_horz,
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enum segment_order *segment_order_vert)
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{
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bool standard_swizzle = false;
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bool display_swizzle = false;
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bool render_swizzle = false;
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switch (swizzle) {
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case DC_SW_4KB_S:
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case DC_SW_64KB_S:
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case DC_SW_VAR_S:
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case DC_SW_4KB_S_X:
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case DC_SW_64KB_S_X:
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case DC_SW_VAR_S_X:
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standard_swizzle = true;
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break;
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case DC_SW_4KB_R:
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case DC_SW_64KB_R:
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case DC_SW_VAR_R:
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case DC_SW_4KB_R_X:
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case DC_SW_64KB_R_X:
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case DC_SW_VAR_R_X:
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render_swizzle = true;
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break;
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case DC_SW_4KB_D:
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case DC_SW_64KB_D:
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case DC_SW_VAR_D:
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case DC_SW_4KB_D_X:
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case DC_SW_64KB_D_X:
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case DC_SW_VAR_D_X:
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display_swizzle = true;
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break;
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default:
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break;
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}
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if (standard_swizzle) {
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if (bytes_per_element == 1) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__na;
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return true;
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}
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if (bytes_per_element == 2) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 4) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 8) {
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*segment_order_horz = segment_order__na;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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}
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if (render_swizzle) {
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if (bytes_per_element == 1) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__na;
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return true;
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}
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if (bytes_per_element == 2) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 4) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__non_contiguous;
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return true;
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}
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if (bytes_per_element == 8) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__non_contiguous;
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return true;
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}
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}
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if (display_swizzle && bytes_per_element == 8) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__non_contiguous;
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return true;
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}
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return false;
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}
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static void hubbub3_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
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unsigned int bytes_per_element)
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{
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/* copied from DML. might want to refactor DML to leverage from DML */
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/* DML : get_blk256_size */
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if (bytes_per_element == 1) {
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*blk256_width = 16;
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*blk256_height = 16;
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} else if (bytes_per_element == 2) {
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*blk256_width = 16;
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*blk256_height = 8;
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} else if (bytes_per_element == 4) {
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*blk256_width = 8;
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*blk256_height = 8;
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} else if (bytes_per_element == 8) {
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*blk256_width = 8;
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*blk256_height = 4;
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}
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}
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static void hubbub3_det_request_size(
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unsigned int detile_buf_size,
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unsigned int height,
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unsigned int width,
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unsigned int bpe,
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bool *req128_horz_wc,
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bool *req128_vert_wc)
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{
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unsigned int blk256_height = 0;
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unsigned int blk256_width = 0;
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unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
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hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe);
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swath_bytes_horz_wc = width * blk256_height * bpe;
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swath_bytes_vert_wc = height * blk256_width * bpe;
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*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
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false : /* full 256B request */
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true; /* half 128b request */
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*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
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false : /* full 256B request */
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true; /* half 128b request */
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}
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bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,
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const struct dc_dcc_surface_param *input,
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struct dc_surface_dcc_cap *output)
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{
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struct dc *dc = hubbub->ctx->dc;
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/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
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enum dcc_control dcc_control;
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unsigned int bpe;
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enum segment_order segment_order_horz, segment_order_vert;
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bool req128_horz_wc, req128_vert_wc;
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memset(output, 0, sizeof(*output));
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if (dc->debug.disable_dcc == DCC_DISABLE)
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return false;
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if (!hubbub->funcs->dcc_support_pixel_format(input->format,
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&bpe))
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return false;
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if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
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&segment_order_horz, &segment_order_vert))
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return false;
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hubbub3_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
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input->surface_size.height, input->surface_size.width,
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bpe, &req128_horz_wc, &req128_vert_wc);
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if (!req128_horz_wc && !req128_vert_wc) {
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dcc_control = dcc_control__256_256_xxx;
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} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
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if (!req128_horz_wc)
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dcc_control = dcc_control__256_256_xxx;
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else if (segment_order_horz == segment_order__contiguous)
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dcc_control = dcc_control__128_128_xxx;
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else
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dcc_control = dcc_control__256_64_64;
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} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
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if (!req128_vert_wc)
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dcc_control = dcc_control__256_256_xxx;
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else if (segment_order_vert == segment_order__contiguous)
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dcc_control = dcc_control__128_128_xxx;
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else
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dcc_control = dcc_control__256_64_64;
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} else {
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if ((req128_horz_wc &&
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segment_order_horz == segment_order__non_contiguous) ||
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(req128_vert_wc &&
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segment_order_vert == segment_order__non_contiguous))
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/* access_dir not known, must use most constraining */
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dcc_control = dcc_control__256_64_64;
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else
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/* reg128 is true for either horz and vert
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* but segment_order is contiguous
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*/
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dcc_control = dcc_control__128_128_xxx;
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}
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/* Exception for 64KB_R_X */
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if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
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dcc_control = dcc_control__128_128_xxx;
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if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
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dcc_control != dcc_control__256_256_xxx)
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return false;
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switch (dcc_control) {
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case dcc_control__256_256_xxx:
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output->grph.rgb.max_uncompressed_blk_size = 256;
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output->grph.rgb.max_compressed_blk_size = 256;
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output->grph.rgb.independent_64b_blks = false;
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output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;
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output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
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break;
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case dcc_control__128_128_xxx:
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output->grph.rgb.max_uncompressed_blk_size = 128;
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output->grph.rgb.max_compressed_blk_size = 128;
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output->grph.rgb.independent_64b_blks = false;
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output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;
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output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
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break;
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case dcc_control__256_64_64:
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output->grph.rgb.max_uncompressed_blk_size = 256;
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output->grph.rgb.max_compressed_blk_size = 64;
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output->grph.rgb.independent_64b_blks = true;
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output->grph.rgb.dcc_controls.dcc_256_64_64 = 1;
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break;
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case dcc_control__256_128_128:
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output->grph.rgb.max_uncompressed_blk_size = 256;
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output->grph.rgb.max_compressed_blk_size = 128;
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output->grph.rgb.independent_64b_blks = false;
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output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
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break;
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}
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output->capable = true;
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output->const_color_support = true;
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return true;
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}
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void hubbub3_force_wm_propagate_to_pipes(struct hubbub *hubbub)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
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uint32_t prog_wm_value = convert_and_clamp(hubbub1->watermarks.a.urgent_ns,
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refclk_mhz, 0x1fffff);
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REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
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DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value,
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DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
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}
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void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
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bool force, bool allow)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
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DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, allow,
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DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, force);
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}
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/* Copy values from WM set A to all other sets */
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void hubbub3_init_watermarks(struct hubbub *hubbub)
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{
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struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
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uint32_t reg;
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reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
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REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
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REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
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REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
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reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
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REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
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REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
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REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
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reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
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REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
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REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
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REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
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reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
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REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
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REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
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REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
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reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
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REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
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REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
|
|
|
|
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
|
|
|
|
reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
|
|
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
|
|
}
|
|
|
|
static const struct hubbub_funcs hubbub30_funcs = {
|
|
.update_dchub = hubbub2_update_dchub,
|
|
.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
|
|
.init_vm_ctx = hubbub2_init_vm_ctx,
|
|
.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
|
|
.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
|
|
.get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
|
|
.wm_read_state = hubbub21_wm_read_state,
|
|
.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
|
|
.program_watermarks = hubbub3_program_watermarks,
|
|
.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
|
|
.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
|
|
.verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high,
|
|
.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
|
|
.force_pstate_change_control = hubbub3_force_pstate_change_control,
|
|
.init_watermarks = hubbub3_init_watermarks,
|
|
.hubbub_read_state = hubbub2_read_state,
|
|
};
|
|
|
|
void hubbub3_construct(struct dcn20_hubbub *hubbub3,
|
|
struct dc_context *ctx,
|
|
const struct dcn_hubbub_registers *hubbub_regs,
|
|
const struct dcn_hubbub_shift *hubbub_shift,
|
|
const struct dcn_hubbub_mask *hubbub_mask)
|
|
{
|
|
hubbub3->base.ctx = ctx;
|
|
hubbub3->base.funcs = &hubbub30_funcs;
|
|
hubbub3->regs = hubbub_regs;
|
|
hubbub3->shifts = hubbub_shift;
|
|
hubbub3->masks = hubbub_mask;
|
|
|
|
hubbub3->debug_test_index_pstate = 0xB;
|
|
hubbub3->detile_buf_size = 184 * 1024; /* 184KB for DCN3 */
|
|
}
|
|
|