359 lines
9.3 KiB
C
359 lines
9.3 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dcn32_dccg.h"
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#define TO_DCN_DCCG(dccg)\
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container_of(dccg, struct dcn_dccg, base)
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#define REG(reg) \
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(dccg_dcn->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
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#define CTX \
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dccg_dcn->base.ctx
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#define DC_LOGGER \
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dccg->ctx->logger
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static void dccg32_get_pixel_rate_div(
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struct dccg *dccg,
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uint32_t otg_inst,
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enum pixel_rate_div *k1,
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enum pixel_rate_div *k2)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;
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*k1 = PIXEL_RATE_DIV_NA;
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*k2 = PIXEL_RATE_DIV_NA;
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switch (otg_inst) {
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case 0:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG0_PIXEL_RATE_DIVK1, &val_k1,
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OTG0_PIXEL_RATE_DIVK2, &val_k2);
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break;
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case 1:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG1_PIXEL_RATE_DIVK1, &val_k1,
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OTG1_PIXEL_RATE_DIVK2, &val_k2);
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break;
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case 2:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG2_PIXEL_RATE_DIVK1, &val_k1,
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OTG2_PIXEL_RATE_DIVK2, &val_k2);
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break;
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case 3:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG3_PIXEL_RATE_DIVK1, &val_k1,
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OTG3_PIXEL_RATE_DIVK2, &val_k2);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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*k1 = (enum pixel_rate_div)val_k1;
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*k2 = (enum pixel_rate_div)val_k2;
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}
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static void dccg32_set_pixel_rate_div(
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struct dccg *dccg,
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uint32_t otg_inst,
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enum pixel_rate_div k1,
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enum pixel_rate_div k2)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA;
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// Don't program 0xF into the register field. Not valid since
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// K1 / K2 field is only 1 / 2 bits wide
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if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {
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BREAK_TO_DEBUGGER();
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return;
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}
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dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);
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if (k1 == cur_k1 && k2 == cur_k2)
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return;
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switch (otg_inst) {
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case 0:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG0_PIXEL_RATE_DIVK1, k1,
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OTG0_PIXEL_RATE_DIVK2, k2);
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break;
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case 1:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG1_PIXEL_RATE_DIVK1, k1,
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OTG1_PIXEL_RATE_DIVK2, k2);
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break;
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case 2:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG2_PIXEL_RATE_DIVK1, k1,
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OTG2_PIXEL_RATE_DIVK2, k2);
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break;
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case 3:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG3_PIXEL_RATE_DIVK1, k1,
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OTG3_PIXEL_RATE_DIVK2, k2);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg32_set_dtbclk_p_src(
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struct dccg *dccg,
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enum streamclk_source src,
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uint32_t otg_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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uint32_t p_src_sel = 0; /* selects dprefclk */
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if (src == DTBCLK0)
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p_src_sel = 2; /* selects dtbclk0 */
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switch (otg_inst) {
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case 0:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P0_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P0_SRC_SEL, p_src_sel,
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DTBCLK_P0_EN, 1);
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break;
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case 1:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P1_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P1_SRC_SEL, p_src_sel,
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DTBCLK_P1_EN, 1);
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break;
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case 2:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P2_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P2_SRC_SEL, p_src_sel,
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DTBCLK_P2_EN, 1);
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break;
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case 3:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P3_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P3_SRC_SEL, p_src_sel,
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DTBCLK_P3_EN, 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
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static void dccg32_set_dtbclk_dto(
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struct dccg *dccg,
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const struct dtbclk_dto_params *params)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* DTO Output Rate / Pixel Rate = 1/4 */
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int req_dtbclk_khz = params->pixclk_khz / 4;
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if (params->ref_dtbclk_khz && req_dtbclk_khz) {
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uint32_t modulo, phase;
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// phase / modulo = dtbclk / dtbclk ref
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modulo = params->ref_dtbclk_khz * 1000;
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phase = req_dtbclk_khz * 1000;
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REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
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REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
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REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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DTBCLK_DTO_ENABLE[params->otg_inst], 1);
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REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
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1, 100);
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/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
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dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
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/* The recommended programming sequence to enable DTBCLK DTO to generate
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* valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
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* be set only after DTO is enabled
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*/
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REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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PIPE_DTO_SRC_SEL[params->otg_inst], 2);
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} else {
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REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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DTBCLK_DTO_ENABLE[params->otg_inst], 0,
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PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);
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REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
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REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
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}
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}
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static void dccg32_set_valid_pixel_rate(
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struct dccg *dccg,
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int ref_dtbclk_khz,
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int otg_inst,
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int pixclk_khz)
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{
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struct dtbclk_dto_params dto_params = {0};
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dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
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dto_params.otg_inst = otg_inst;
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dto_params.pixclk_khz = pixclk_khz;
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dto_params.is_hdmi = true;
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dccg32_set_dtbclk_dto(dccg, &dto_params);
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}
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static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
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unsigned int xtalin_freq_inKhz,
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unsigned int *dccg_ref_freq_inKhz)
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{
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/*
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* Assume refclk is sourced from xtalin
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* expect 100MHz
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*/
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*dccg_ref_freq_inKhz = xtalin_freq_inKhz;
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return;
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}
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static void dccg32_set_dpstreamclk(
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struct dccg *dccg,
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enum streamclk_source src,
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int otg_inst,
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int dp_hpo_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* set the dtbclk_p source */
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dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
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/* enabled to select one of the DTBCLKs for pipe */
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switch (dp_hpo_inst) {
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case 0:
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REG_UPDATE_2(DPSTREAMCLK_CNTL,
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DPSTREAMCLK0_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);
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break;
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case 1:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);
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break;
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case 2:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);
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break;
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case 3:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg32_otg_add_pixel(struct dccg *dccg,
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uint32_t otg_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
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OTG_ADD_PIXEL[otg_inst], 1);
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}
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static void dccg32_otg_drop_pixel(struct dccg *dccg,
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uint32_t otg_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
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OTG_DROP_PIXEL[otg_inst], 1);
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}
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static const struct dccg_funcs dccg32_funcs = {
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.update_dpp_dto = dccg2_update_dpp_dto,
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.get_dccg_ref_freq = dccg32_get_dccg_ref_freq,
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.dccg_init = dccg31_init,
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.set_dpstreamclk = dccg32_set_dpstreamclk,
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.enable_symclk32_se = dccg31_enable_symclk32_se,
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.disable_symclk32_se = dccg31_disable_symclk32_se,
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.enable_symclk32_le = dccg31_enable_symclk32_le,
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.disable_symclk32_le = dccg31_disable_symclk32_le,
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.set_physymclk = dccg31_set_physymclk,
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.set_dtbclk_dto = dccg32_set_dtbclk_dto,
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.set_valid_pixel_rate = dccg32_set_valid_pixel_rate,
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.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
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.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
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.otg_add_pixel = dccg32_otg_add_pixel,
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.otg_drop_pixel = dccg32_otg_drop_pixel,
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.set_pixel_rate_div = dccg32_set_pixel_rate_div,
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};
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struct dccg *dccg32_create(
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struct dc_context *ctx,
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const struct dccg_registers *regs,
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const struct dccg_shift *dccg_shift,
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const struct dccg_mask *dccg_mask)
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{
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struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
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struct dccg *base;
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if (dccg_dcn == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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base = &dccg_dcn->base;
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base->ctx = ctx;
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base->funcs = &dccg32_funcs;
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dccg_dcn->regs = regs;
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dccg_dcn->dccg_shift = dccg_shift;
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dccg_dcn->dccg_mask = dccg_mask;
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return &dccg_dcn->base;
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}
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