215 lines
7.2 KiB
C
215 lines
7.2 KiB
C
/*
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* Copyright 2012-20 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dce_calcs.h"
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#include "reg_helper.h"
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#include "basics/conversion.h"
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#include "dcn32_hubp.h"
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#define REG(reg)\
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hubp2->hubp_regs->reg
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#define CTX \
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hubp2->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
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void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_UPDATE_2(UCLK_PSTATE_FORCE,
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DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow,
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DATA_UCLK_PSTATE_FORCE_VALUE, 0);
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}
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void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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// Also cache cursor in MALL if using MALL for SS
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REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
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USE_MALL_FOR_CURSOR, c_cursor);
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}
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void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable);
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/* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP:
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* For Pstate change using the MALL with sub-viewport buffering,
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* the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored)
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* and sub-viewport positioning by Display FW has to avoid the cursor
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* requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion).
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*
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* CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch.
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* Setting this should allow the sub-viewport position to always avoid the cursor because
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* we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank).
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*/
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REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);
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}
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void hubp32_phantom_hubp_post_enable(struct hubp *hubp)
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{
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uint32_t reg_val;
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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/* For phantom pipe enable, disable GSL */
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REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, 0);
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REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1);
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reg_val = REG_READ(DCHUBP_CNTL);
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if (reg_val) {
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/* init sequence workaround: in case HUBP is
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* power gated, this wait would timeout.
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*
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* we just wrote reg_val to non-0, if it stay 0
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* it means HUBP is gated
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*/
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REG_WAIT(DCHUBP_CNTL,
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HUBP_NO_OUTSTANDING_REQ, 1,
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1, 200);
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}
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}
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void hubp32_cursor_set_attributes(
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struct hubp *hubp,
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const struct dc_cursor_attributes *attr)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
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enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
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attr->width, attr->color_format);
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//Round cursor width up to next multiple of 64
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uint32_t cursor_width = ((attr->width + 63) / 64) * 64;
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uint32_t cursor_height = attr->height;
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uint32_t cursor_size = cursor_width * cursor_height;
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hubp->curs_attr = *attr;
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REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
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CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
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REG_UPDATE(CURSOR_SURFACE_ADDRESS,
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CURSOR_SURFACE_ADDRESS, attr->address.low_part);
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REG_UPDATE_2(CURSOR_SIZE,
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CURSOR_WIDTH, attr->width,
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CURSOR_HEIGHT, attr->height);
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REG_UPDATE_4(CURSOR_CONTROL,
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CURSOR_MODE, attr->color_format,
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CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
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CURSOR_PITCH, hw_pitch,
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CURSOR_LINES_PER_CHUNK, lpc);
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REG_SET_2(CURSOR_SETTINGS, 0,
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/* no shift of the cursor HDL schedule */
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CURSOR0_DST_Y_OFFSET, 0,
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/* used to shift the cursor chunk request deadline */
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CURSOR0_CHUNK_HDL_ADJUST, 3);
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switch (attr->color_format) {
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case CURSOR_MODE_MONO:
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cursor_size /= 2;
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break;
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case CURSOR_MODE_COLOR_1BIT_AND:
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case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
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case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
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cursor_size *= 4;
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break;
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case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
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case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
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default:
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cursor_size *= 8;
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break;
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}
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if (cursor_size > 16384)
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REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);
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else
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REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);
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}
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void hubp32_init(struct hubp *hubp)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
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}
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static struct hubp_funcs dcn32_hubp_funcs = {
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.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
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.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
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.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
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.hubp_program_surface_config = hubp3_program_surface_config,
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.hubp_is_flip_pending = hubp2_is_flip_pending,
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.hubp_setup = hubp3_setup,
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.hubp_setup_interdependent = hubp2_setup_interdependent,
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.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
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.set_blank = hubp2_set_blank,
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.dcc_control = hubp3_dcc_control,
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.mem_program_viewport = min_set_viewport,
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.set_cursor_attributes = hubp32_cursor_set_attributes,
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.set_cursor_position = hubp2_cursor_set_position,
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.hubp_clk_cntl = hubp2_clk_cntl,
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.hubp_vtg_sel = hubp2_vtg_sel,
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.dmdata_set_attributes = hubp3_dmdata_set_attributes,
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.dmdata_load = hubp2_dmdata_load,
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.dmdata_status_done = hubp2_dmdata_status_done,
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.hubp_read_state = hubp3_read_state,
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.hubp_clear_underflow = hubp2_clear_underflow,
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.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
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.hubp_init = hubp3_init,
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.set_unbounded_requesting = hubp31_set_unbounded_requesting,
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.hubp_soft_reset = hubp31_soft_reset,
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.hubp_set_flip_int = hubp1_set_flip_int,
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.hubp_in_blank = hubp1_in_blank,
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.hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow,
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.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
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.hubp_update_mall_sel = hubp32_update_mall_sel,
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.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering
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};
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bool hubp32_construct(
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struct dcn20_hubp *hubp2,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn_hubp2_registers *hubp_regs,
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const struct dcn_hubp2_shift *hubp_shift,
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const struct dcn_hubp2_mask *hubp_mask)
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{
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hubp2->base.funcs = &dcn32_hubp_funcs;
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hubp2->base.ctx = ctx;
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hubp2->hubp_regs = hubp_regs;
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hubp2->hubp_shift = hubp_shift;
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hubp2->hubp_mask = hubp_mask;
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hubp2->base.inst = inst;
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hubp2->base.opp_id = OPP_ID_INVALID;
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hubp2->base.mpcc_id = 0xf;
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return true;
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}
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