202 lines
5.5 KiB
C
202 lines
5.5 KiB
C
/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
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#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
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#include "gpio_regs.h"
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/****************************** new register headers */
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/*** following in header */
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#define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \
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.type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
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.type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
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.type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT
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#define DDC_GPIO_REG_LIST(cd,id) \
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{\
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DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
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DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\
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DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\
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DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\
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}
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#define DDC_REG_LIST(cd,id) \
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DDC_GPIO_REG_LIST(cd,id),\
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.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
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#define DDC_REG_LIST_DCN2(cd, id) \
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DDC_GPIO_REG_LIST(cd, id),\
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.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
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.phy_aux_cntl = REG(PHY_AUX_CNTL), \
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.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
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#define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
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.type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
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.type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
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.type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT
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#define DDC_GPIO_VGA_REG_LIST(cd) \
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{\
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DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
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DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\
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DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\
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DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\
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}
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#define DDC_VGA_REG_LIST(cd) \
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DDC_GPIO_VGA_REG_LIST(cd),\
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.ddc_setup = mmDC_I2C_DDCVGA_SETUP
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#define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \
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.type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
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.type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
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.type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT
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#define DDC_GPIO_I2C_REG_LIST(cd) \
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{\
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DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
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DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\
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DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\
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DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\
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}
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#define DDC_I2C_REG_LIST(cd) \
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DDC_GPIO_I2C_REG_LIST(cd),\
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.ddc_setup = 0
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#define DDC_I2C_REG_LIST_DCN2(cd) \
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DDC_GPIO_I2C_REG_LIST(cd),\
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.ddc_setup = 0,\
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.phy_aux_cntl = REG(PHY_AUX_CNTL), \
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.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
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#define DDC_MASK_SH_LIST_COMMON(mask_sh) \
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SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
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SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
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SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\
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SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\
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SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\
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SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh)
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#define DDC_MASK_SH_LIST(mask_sh) \
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DDC_MASK_SH_LIST_COMMON(mask_sh),\
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SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
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SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
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#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
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{DDC_MASK_SH_LIST_COMMON(mask_sh),\
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0,\
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0,\
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(PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
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(DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
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#define DDC_MASK_SH_LIST_DCN2_VGA(mask_sh) \
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{DDC_MASK_SH_LIST_COMMON(mask_sh),\
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0,\
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0,\
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0,\
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0}
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struct ddc_registers {
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struct gpio_registers gpio;
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uint32_t ddc_setup;
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uint32_t phy_aux_cntl;
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uint32_t dc_gpio_aux_ctrl_5;
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};
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struct ddc_sh_mask {
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/* i2c_dd_setup */
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uint32_t DC_I2C_DDC1_ENABLE;
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uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE;
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uint32_t DC_I2C_DDC1_EDID_DETECT_MODE;
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/* ddc1_mask */
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uint32_t DC_GPIO_DDC1DATA_PD_EN;
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uint32_t DC_GPIO_DDC1CLK_PD_EN;
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uint32_t AUX_PAD1_MODE;
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/* i2cpad_mask */
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uint32_t DC_GPIO_SDA_PD_DIS;
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uint32_t DC_GPIO_SCL_PD_DIS;
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//phy_aux_cntl
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uint32_t AUX_PAD_RXSEL;
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uint32_t DDC_PAD_I2CMODE;
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};
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/*** following in dc_resource */
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#define ddc_data_regs(id) \
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{\
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DDC_REG_LIST(DATA,id)\
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}
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#define ddc_clk_regs(id) \
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{\
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DDC_REG_LIST(CLK,id)\
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}
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#define ddc_vga_data_regs \
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{\
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DDC_VGA_REG_LIST(DATA)\
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}
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#define ddc_vga_clk_regs \
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{\
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DDC_VGA_REG_LIST(CLK)\
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}
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#define ddc_i2c_data_regs \
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{\
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DDC_I2C_REG_LIST(SDA)\
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}
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#define ddc_i2c_clk_regs \
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{\
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DDC_I2C_REG_LIST(SCL)\
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}
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#define ddc_data_regs_dcn2(id) \
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{\
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DDC_REG_LIST_DCN2(DATA, id)\
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}
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#define ddc_clk_regs_dcn2(id) \
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{\
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DDC_REG_LIST_DCN2(CLK, id)\
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}
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#define ddc_i2c_data_regs_dcn2 \
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{\
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DDC_I2C_REG_LIST_DCN2(SDA)\
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}
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#define ddc_i2c_clk_regs_dcn2 \
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{\
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DDC_REG_LIST_DCN2(SCL)\
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}
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#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */
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