191 lines
5.8 KiB
C
191 lines
5.8 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_CLOCK_SOURCE_H__
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#define __DC_CLOCK_SOURCE_H__
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#include "dc_types.h"
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#include "include/grph_object_id.h"
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#include "include/bios_parser_types.h"
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struct clock_source;
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struct spread_spectrum_data {
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uint32_t percentage; /*> In unit of 0.01% or 0.001%*/
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uint32_t percentage_divider; /*> 100 or 1000 */
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uint32_t freq_range_khz;
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uint32_t modulation_freq_hz;
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struct spread_spectrum_flags flags;
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};
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struct delta_sigma_data {
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uint32_t feedback_amount;
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uint32_t nfrac_amount;
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uint32_t ds_frac_size;
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uint32_t ds_frac_amount;
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};
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/**
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* Pixel Clock Parameters structure
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* These parameters are required as input
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* when calculating Pixel Clock Dividers for requested Pixel Clock
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*/
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struct pixel_clk_flags {
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uint32_t ENABLE_SS:1;
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uint32_t DISPLAY_BLANKED:1;
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uint32_t PROGRAM_PIXEL_CLOCK:1;
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uint32_t PROGRAM_ID_CLOCK:1;
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uint32_t SUPPORT_YCBCR420:1;
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};
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/**
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* Display Port HW De spread of Reference Clock related Parameters structure
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* Store it once at boot for later usage
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*/
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struct csdp_ref_clk_ds_params {
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bool hw_dso_n_dp_ref_clk;
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/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
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uint32_t avg_dp_ref_clk_khz;
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/* Average DP Reference clock (in KHz)*/
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uint32_t ss_percentage_on_dp_ref_clk;
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/* DP Reference clock SS percentage
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* (not to be mixed with DP IDCLK SS from PLL Settings)*/
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uint32_t ss_percentage_divider;
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/* DP Reference clock SS percentage divider */
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};
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struct pixel_clk_params {
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uint32_t requested_pix_clk_100hz;
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/*> Requested Pixel Clock
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* (based on Video Timing standard used for requested mode)*/
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uint32_t requested_sym_clk; /* in KHz */
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/*> Requested Sym Clock (relevant only for display port)*/
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uint32_t dp_ref_clk; /* in KHz */
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/*> DP reference clock - calculated only for DP signal for specific cases*/
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struct graphics_object_id encoder_object_id;
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/*> Encoder object Id - needed by VBIOS Exec table*/
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enum signal_type signal_type;
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/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
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enum controller_id controller_id;
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/*> ControllerId - which controller using this PLL*/
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enum dc_color_depth color_depth;
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struct csdp_ref_clk_ds_params de_spread_params;
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/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
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enum dc_pixel_encoding pixel_encoding;
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struct pixel_clk_flags flags;
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};
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/**
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* Pixel Clock Dividers structure with desired Pixel Clock
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* (adjusted after VBIOS exec table),
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* with actually calculated Clock and reference Crystal frequency
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*/
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struct pll_settings {
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uint32_t actual_pix_clk_100hz;
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uint32_t adjusted_pix_clk_100hz;
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uint32_t calculated_pix_clk_100hz;
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uint32_t vco_freq;
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uint32_t reference_freq;
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uint32_t reference_divider;
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uint32_t feedback_divider;
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uint32_t fract_feedback_divider;
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uint32_t pix_clk_post_divider;
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uint32_t ss_percentage;
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bool use_external_clk;
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};
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struct calc_pll_clock_source_init_data {
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struct dc_bios *bp;
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uint32_t min_pix_clk_pll_post_divider;
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uint32_t max_pix_clk_pll_post_divider;
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uint32_t min_pll_ref_divider;
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uint32_t max_pll_ref_divider;
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uint32_t min_override_input_pxl_clk_pll_freq_khz;
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/* if not 0, override the firmware info */
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uint32_t max_override_input_pxl_clk_pll_freq_khz;
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/* if not 0, override the firmware info */
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uint32_t num_fract_fb_divider_decimal_point;
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/* number of decimal point for fractional feedback divider value */
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uint32_t num_fract_fb_divider_decimal_point_precision;
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/* number of decimal point to round off for fractional feedback divider value*/
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struct dc_context *ctx;
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};
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struct calc_pll_clock_source {
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uint32_t ref_freq_khz;
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uint32_t min_pix_clock_pll_post_divider;
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uint32_t max_pix_clock_pll_post_divider;
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uint32_t min_pll_ref_divider;
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uint32_t max_pll_ref_divider;
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uint32_t max_vco_khz;
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uint32_t min_vco_khz;
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uint32_t min_pll_input_freq_khz;
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uint32_t max_pll_input_freq_khz;
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uint32_t fract_fb_divider_decimal_points_num;
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uint32_t fract_fb_divider_factor;
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uint32_t fract_fb_divider_precision;
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uint32_t fract_fb_divider_precision_factor;
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struct dc_context *ctx;
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};
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struct clock_source_funcs {
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bool (*cs_power_down)(
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struct clock_source *);
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bool (*program_pix_clk)(
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struct clock_source *,
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struct pixel_clk_params *,
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enum dp_link_encoding encoding,
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struct pll_settings *);
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uint32_t (*get_pix_clk_dividers)(
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struct clock_source *,
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struct pixel_clk_params *,
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struct pll_settings *);
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bool (*get_pixel_clk_frequency_100hz)(
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const struct clock_source *clock_source,
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unsigned int inst,
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unsigned int *pixel_clk_khz);
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bool (*override_dp_pix_clk)(
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struct clock_source *clock_source,
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unsigned int inst,
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unsigned int pixel_clk,
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unsigned int ref_clk);
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};
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struct clock_source {
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const struct clock_source_funcs *funcs;
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struct dc_context *ctx;
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enum clock_source_id id;
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bool dp_clk_src;
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};
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#endif
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