399 lines
13 KiB
C
399 lines
13 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/* FILE POLICY AND INTENDED USAGE:
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* This file owns timing validation against various link limitations. (ex.
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* link bandwidth, receiver capability or our hardware capability) It also
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* provides helper functions exposing bandwidth formulas used in validation.
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*/
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#include "link_validation.h"
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#include "resource.h"
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#define DC_LOGGER_INIT(logger)
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static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing)
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{
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uint32_t pxl_clk = timing->pix_clk_100hz;
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if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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pxl_clk /= 2;
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else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
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pxl_clk = pxl_clk * 2 / 3;
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if (timing->display_color_depth == COLOR_DEPTH_101010)
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pxl_clk = pxl_clk * 10 / 8;
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else if (timing->display_color_depth == COLOR_DEPTH_121212)
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pxl_clk = pxl_clk * 12 / 8;
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return pxl_clk;
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}
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static bool dp_active_dongle_validate_timing(
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const struct dc_crtc_timing *timing,
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const struct dpcd_caps *dpcd_caps)
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{
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const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
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switch (dpcd_caps->dongle_type) {
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case DISPLAY_DONGLE_DP_VGA_CONVERTER:
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case DISPLAY_DONGLE_DP_DVI_CONVERTER:
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case DISPLAY_DONGLE_DP_DVI_DONGLE:
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if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
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return true;
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else
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return false;
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default:
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break;
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}
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if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
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dongle_caps->extendedCapValid == true) {
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/* Check Pixel Encoding */
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switch (timing->pixel_encoding) {
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case PIXEL_ENCODING_RGB:
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case PIXEL_ENCODING_YCBCR444:
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break;
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case PIXEL_ENCODING_YCBCR422:
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if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
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return false;
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break;
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case PIXEL_ENCODING_YCBCR420:
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if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
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return false;
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break;
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default:
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/* Invalid Pixel Encoding*/
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return false;
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}
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switch (timing->display_color_depth) {
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case COLOR_DEPTH_666:
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case COLOR_DEPTH_888:
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/*888 and 666 should always be supported*/
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break;
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case COLOR_DEPTH_101010:
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if (dongle_caps->dp_hdmi_max_bpc < 10)
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return false;
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break;
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case COLOR_DEPTH_121212:
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if (dongle_caps->dp_hdmi_max_bpc < 12)
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return false;
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break;
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case COLOR_DEPTH_141414:
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case COLOR_DEPTH_161616:
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default:
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/* These color depths are currently not supported */
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return false;
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}
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/* Check 3D format */
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switch (timing->timing_3d_format) {
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case TIMING_3D_FORMAT_NONE:
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case TIMING_3D_FORMAT_FRAME_ALTERNATE:
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/*Only frame alternate 3D is supported on active dongle*/
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break;
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default:
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/*other 3D formats are not supported due to bad infoframe translation */
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return false;
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}
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if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
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struct dc_crtc_timing outputTiming = *timing;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
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/* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
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outputTiming.flags.DSC = 0;
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#endif
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if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
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return false;
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} else { // DP to HDMI TMDS converter
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if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
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return false;
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}
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}
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if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
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dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
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dongle_caps->dfp_cap_ext.supported) {
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if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
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return false;
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if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
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return false;
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if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
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return false;
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if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
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if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
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return false;
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if (timing->display_color_depth == COLOR_DEPTH_666 &&
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!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_888 &&
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!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
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!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
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!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
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!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
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return false;
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} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
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if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
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return false;
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if (timing->display_color_depth == COLOR_DEPTH_888 &&
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!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
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!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
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!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
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!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
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return false;
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} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
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if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
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return false;
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if (timing->display_color_depth == COLOR_DEPTH_888 &&
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!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
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!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
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!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
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!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
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return false;
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} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
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if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
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return false;
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if (timing->display_color_depth == COLOR_DEPTH_888 &&
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!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
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!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
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!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
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return false;
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else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
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!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
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return false;
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}
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}
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return true;
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}
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uint32_t dp_link_bandwidth_kbps(
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const struct dc_link *link,
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const struct dc_link_settings *link_settings)
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{
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uint32_t total_data_bw_efficiency_x10000 = 0;
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uint32_t link_rate_per_lane_kbps = 0;
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switch (link_dp_get_encoding_format(link_settings)) {
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case DP_8b_10b_ENCODING:
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/* For 8b/10b encoding:
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* link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
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* data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
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*/
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link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
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total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
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if (dc_link_should_enable_fec(link)) {
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total_data_bw_efficiency_x10000 /= 100;
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total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
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}
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break;
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case DP_128b_132b_ENCODING:
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/* For 128b/132b encoding:
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* link rate is defined in the unit of 10mbps per lane.
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* total data bandwidth efficiency is always 96.71%.
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*/
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link_rate_per_lane_kbps = link_settings->link_rate * 10000;
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total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
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break;
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default:
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break;
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}
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/* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
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return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000;
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}
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uint32_t link_timing_bandwidth_kbps(
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const struct dc_crtc_timing *timing)
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{
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uint32_t bits_per_channel = 0;
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uint32_t kbps;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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if (timing->flags.DSC)
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return dc_dsc_stream_bandwidth_in_kbps(timing,
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timing->dsc_cfg.bits_per_pixel,
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timing->dsc_cfg.num_slices_h,
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timing->dsc_cfg.is_dp);
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#endif /* CONFIG_DRM_AMD_DC_DCN */
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switch (timing->display_color_depth) {
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case COLOR_DEPTH_666:
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bits_per_channel = 6;
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break;
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case COLOR_DEPTH_888:
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bits_per_channel = 8;
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break;
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case COLOR_DEPTH_101010:
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bits_per_channel = 10;
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break;
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case COLOR_DEPTH_121212:
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bits_per_channel = 12;
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break;
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case COLOR_DEPTH_141414:
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bits_per_channel = 14;
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break;
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case COLOR_DEPTH_161616:
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bits_per_channel = 16;
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break;
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default:
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ASSERT(bits_per_channel != 0);
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bits_per_channel = 8;
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break;
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}
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kbps = timing->pix_clk_100hz / 10;
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kbps *= bits_per_channel;
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if (timing->flags.Y_ONLY != 1) {
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/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
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kbps *= 3;
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if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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kbps /= 2;
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else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
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kbps = kbps * 2 / 3;
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}
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return kbps;
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}
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static bool dp_validate_mode_timing(
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struct dc_link *link,
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const struct dc_crtc_timing *timing)
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{
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uint32_t req_bw;
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uint32_t max_bw;
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const struct dc_link_settings *link_setting;
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/* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
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if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
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!link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
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dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
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return false;
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/*always DP fail safe mode*/
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if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
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timing->h_addressable == (uint32_t) 640 &&
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timing->v_addressable == (uint32_t) 480)
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return true;
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link_setting = dc_link_get_link_cap(link);
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/* TODO: DYNAMIC_VALIDATION needs to be implemented */
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/*if (flags.DYNAMIC_VALIDATION == 1 &&
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link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
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link_setting = &link->verified_link_cap;
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*/
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req_bw = dc_bandwidth_in_kbps_from_timing(timing);
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max_bw = dc_link_bandwidth_kbps(link, link_setting);
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if (req_bw <= max_bw) {
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/* remember the biggest mode here, during
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* initial link training (to get
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* verified_link_cap), LS sends event about
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* cannot train at reported cap to upper
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* layer and upper layer will re-enumerate modes.
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* this is not necessary if the lower
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* verified_link_cap is enough to drive
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* all the modes */
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/* TODO: DYNAMIC_VALIDATION needs to be implemented */
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/* if (flags.DYNAMIC_VALIDATION == 1)
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dpsst->max_req_bw_for_verified_linkcap = dal_max(
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dpsst->max_req_bw_for_verified_linkcap, req_bw); */
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return true;
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} else
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return false;
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}
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enum dc_status link_validate_mode_timing(
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const struct dc_stream_state *stream,
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struct dc_link *link,
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const struct dc_crtc_timing *timing)
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{
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uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
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struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
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/* A hack to avoid failing any modes for EDID override feature on
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* topology change such as lower quality cable for DP or different dongle
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*/
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if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
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return DC_OK;
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/* Passive Dongle */
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if (max_pix_clk != 0 && get_tmds_output_pixel_clock_100hz(timing) > max_pix_clk)
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return DC_EXCEED_DONGLE_CAP;
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/* Active Dongle*/
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if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
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return DC_EXCEED_DONGLE_CAP;
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switch (stream->signal) {
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case SIGNAL_TYPE_EDP:
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case SIGNAL_TYPE_DISPLAY_PORT:
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if (!dp_validate_mode_timing(
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link,
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timing))
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return DC_NO_DP_LINK_BANDWIDTH;
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break;
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default:
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break;
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}
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return DC_OK;
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}
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