123 lines
3.6 KiB
C
123 lines
3.6 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "soc15.h"
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#include "soc15_hw_ip.h"
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#include "soc15_common.h"
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#include "vega20_inc.h"
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#include "vega20_ppsmc.h"
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#include "vega20_baco.h"
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#include "vega20_smumgr.h"
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#include "amdgpu_ras.h"
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static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
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{
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{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
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{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
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};
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int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
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uint32_t reg;
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*cap = false;
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if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
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return 0;
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if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
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reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
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if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
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*cap = true;
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}
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return 0;
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}
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int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
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uint32_t reg;
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reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
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if (reg & BACO_CNTL__BACO_MODE_MASK)
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/* gfx has already entered BACO state */
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*state = BACO_STATE_IN;
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else
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*state = BACO_STATE_OUT;
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return 0;
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}
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int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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enum BACO_STATE cur_state;
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uint32_t data;
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vega20_baco_get_state(hwmgr, &cur_state);
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if (cur_state == state)
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/* aisc already in the target state */
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return 0;
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if (state == BACO_STATE_IN) {
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if (!ras || !adev->ras_enabled) {
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
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data |= 0x80000000;
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
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if(smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_EnterBaco, 0, NULL))
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return -EINVAL;
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} else {
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if(smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_EnterBaco, 1, NULL))
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return -EINVAL;
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}
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} else if (state == BACO_STATE_OUT) {
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if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco, NULL))
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return -EINVAL;
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if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
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ARRAY_SIZE(clean_baco_tbl)))
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return -EINVAL;
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}
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return 0;
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}
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int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
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{
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int ret = 0;
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ret = vega20_set_pptable_driver_address(hwmgr);
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if (ret)
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return ret;
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return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, NULL);
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}
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