784 lines
22 KiB
C
784 lines
22 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU72_DISCRETE_H
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#define SMU72_DISCRETE_H
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#include "smu72.h"
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#if !defined(SMC_MICROCODE)
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#pragma pack(push, 1)
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#endif
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struct SMIO_Pattern {
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uint16_t Voltage;
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uint8_t Smio;
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uint8_t padding;
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};
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typedef struct SMIO_Pattern SMIO_Pattern;
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struct SMIO_Table {
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SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
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};
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typedef struct SMIO_Table SMIO_Table;
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struct SMU72_Discrete_GraphicsLevel {
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SMU_VoltageLevel MinVoltage;
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uint32_t SclkFrequency;
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uint8_t pcieDpmLevel;
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uint8_t DeepSleepDivId;
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uint16_t ActivityLevel;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t SpllSpreadSpectrum;
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uint32_t SpllSpreadSpectrum2;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t EnabledForActivity;
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uint8_t EnabledForThrottle;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t PowerThrottle;
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};
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typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
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struct SMU72_Discrete_ACPILevel {
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uint32_t Flags;
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SMU_VoltageLevel MinVoltage;
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uint32_t SclkFrequency;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t DeepSleepDivId;
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uint8_t padding;
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uint32_t CgSpllFuncCntl;
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uint32_t CgSpllFuncCntl2;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t SpllSpreadSpectrum;
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uint32_t SpllSpreadSpectrum2;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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};
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typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
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struct SMU72_Discrete_Ulv {
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint16_t VddcOffset;
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uint8_t VddcOffsetVid;
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uint8_t VddcPhase;
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uint32_t Reserved;
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};
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typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
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struct SMU72_Discrete_MemoryLevel {
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SMU_VoltageLevel MinVoltage;
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uint32_t MinMvdd;
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uint32_t MclkFrequency;
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uint8_t EdcReadEnable;
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uint8_t EdcWriteEnable;
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uint8_t RttEnable;
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uint8_t StutterEnable;
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uint8_t StrobeEnable;
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uint8_t StrobeRatio;
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uint8_t EnabledForThrottle;
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uint8_t EnabledForActivity;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t padding;
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uint16_t ActivityLevel;
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uint8_t DisplayWatermark;
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uint8_t padding1;
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uint32_t MpllFuncCntl;
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uint32_t MpllFuncCntl_1;
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uint32_t MpllFuncCntl_2;
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uint32_t MpllAdFuncCntl;
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uint32_t MpllDqFuncCntl;
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uint32_t MclkPwrmgtCntl;
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uint32_t DllCntl;
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uint32_t MpllSs1;
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uint32_t MpllSs2;
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};
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typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
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struct SMU72_Discrete_LinkLevel {
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uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
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uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
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uint8_t EnabledForActivity;
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uint8_t SPC;
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uint32_t DownThreshold;
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uint32_t UpThreshold;
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uint32_t Reserved;
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};
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typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
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/* MC ARB DRAM Timing registers. */
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struct SMU72_Discrete_MCArbDramTimingTableEntry {
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uint32_t McArbDramTiming;
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uint32_t McArbDramTiming2;
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uint8_t McArbBurstTime;
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uint8_t padding[3];
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};
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typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
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struct SMU72_Discrete_MCArbDramTimingTable {
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SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
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};
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typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
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/* UVD VCLK/DCLK state (level) definition. */
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struct SMU72_Discrete_UvdLevel {
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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SMU_VoltageLevel MinVoltage;
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uint8_t VclkDivider;
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uint8_t DclkDivider;
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uint8_t padding[2];
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};
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typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
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/* Clocks for other external blocks (VCE, ACP, SAMU). */
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struct SMU72_Discrete_ExtClkLevel {
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uint32_t Frequency;
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SMU_VoltageLevel MinVoltage;
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uint8_t Divider;
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uint8_t padding[3];
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};
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typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
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struct SMU72_Discrete_StateInfo {
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uint32_t SclkFrequency;
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uint32_t MclkFrequency;
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint32_t SamclkFrequency;
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uint32_t AclkFrequency;
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uint32_t EclkFrequency;
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uint16_t MvddVoltage;
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uint16_t padding16;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint8_t McRegIndex;
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uint8_t SeqIndex;
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uint8_t SclkDid;
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int8_t SclkIndex;
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int8_t MclkIndex;
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uint8_t PCIeGen;
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};
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typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
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struct SMU72_Discrete_DpmTable {
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/* Multi-DPM controller settings */
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SMU72_PIDController GraphicsPIDController;
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SMU72_PIDController MemoryPIDController;
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SMU72_PIDController LinkPIDController;
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uint32_t SystemFlags;
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/* SMIO masks for voltage and phase controls */
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uint32_t VRConfig;
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uint32_t SmioMask1;
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uint32_t SmioMask2;
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SMIO_Table SmioTable1;
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SMIO_Table SmioTable2;
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uint32_t VddcLevelCount;
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uint32_t VddciLevelCount;
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uint32_t VddGfxLevelCount;
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uint32_t MvddLevelCount;
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uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC];
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uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
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uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI];
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uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
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uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
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uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
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uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
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uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
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uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
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uint8_t GraphicsDpmLevelCount;
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uint8_t MemoryDpmLevelCount;
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uint8_t LinkLevelCount;
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uint8_t MasterDeepSleepControl;
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uint8_t UvdLevelCount;
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uint8_t VceLevelCount;
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uint8_t AcpLevelCount;
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uint8_t SamuLevelCount;
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uint8_t ThermOutGpio;
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uint8_t ThermOutPolarity;
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uint8_t ThermOutMode;
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uint8_t DPMFreezeAndForced;
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uint32_t Reserved[4];
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/* State table entries for each DPM state */
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SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
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SMU72_Discrete_MemoryLevel MemoryACPILevel;
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SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
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SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK];
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SMU72_Discrete_ACPILevel ACPILevel;
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SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD];
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SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE];
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SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP];
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SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU];
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SMU72_Discrete_Ulv Ulv;
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uint32_t SclkStepSize;
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uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];
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uint8_t UvdBootLevel;
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uint8_t VceBootLevel;
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uint8_t AcpBootLevel;
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uint8_t SamuBootLevel;
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uint8_t GraphicsBootLevel;
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uint8_t GraphicsVoltageChangeEnable;
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uint8_t GraphicsThermThrottleEnable;
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uint8_t GraphicsInterval;
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uint8_t VoltageInterval;
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uint8_t ThermalInterval;
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uint16_t TemperatureLimitHigh;
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uint16_t TemperatureLimitLow;
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uint8_t MemoryBootLevel;
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uint8_t MemoryVoltageChangeEnable;
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uint16_t BootMVdd;
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uint8_t MemoryInterval;
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uint8_t MemoryThermThrottleEnable;
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uint16_t VoltageResponseTime;
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uint16_t PhaseResponseTime;
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uint8_t PCIeBootLinkLevel;
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uint8_t PCIeGenInterval;
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uint8_t DTEInterval;
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uint8_t DTEMode;
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uint8_t SVI2Enable;
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uint8_t VRHotGpio;
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uint8_t AcDcGpio;
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uint8_t ThermGpio;
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uint16_t PPM_PkgPwrLimit;
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uint16_t PPM_TemperatureLimit;
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uint16_t DefaultTdp;
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uint16_t TargetTdp;
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uint16_t FpsHighThreshold;
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uint16_t FpsLowThreshold;
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uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
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uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
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uint8_t DTEAmbientTempBase;
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uint8_t DTETjOffset;
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uint8_t GpuTjMax;
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uint8_t GpuTjHyst;
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SMU_VoltageLevel BootVoltage;
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uint32_t BAPM_TEMP_GRADIENT;
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uint32_t LowSclkInterruptThreshold;
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uint32_t VddGfxReChkWait;
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uint8_t ClockStretcherAmount;
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uint8_t Sclk_CKS_masterEn0_7;
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uint8_t Sclk_CKS_masterEn8_15;
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uint8_t padding[1];
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uint8_t Sclk_voltageOffset[8];
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SMU_ClockStretcherDataTable ClockStretcherDataTable;
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SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
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};
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typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
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/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
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#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
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#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
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struct SMU72_Discrete_MCRegisterAddress {
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uint16_t s0;
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uint16_t s1;
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};
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typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
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struct SMU72_Discrete_MCRegisterSet {
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uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
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struct SMU72_Discrete_MCRegisters {
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uint8_t last;
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uint8_t reserved[3];
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SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
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};
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typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
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/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
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struct SMU72_Discrete_FanTable {
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uint16_t FdoMode;
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int16_t TempMin;
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int16_t TempMed;
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int16_t TempMax;
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int16_t Slope1;
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int16_t Slope2;
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int16_t FdoMin;
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int16_t HystUp;
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int16_t HystDown;
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int16_t HystSlope;
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int16_t TempRespLim;
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int16_t TempCurr;
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int16_t SlopeCurr;
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int16_t PwmCurr;
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uint32_t RefreshPeriod;
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int16_t FdoMax;
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uint8_t TempSrc;
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int8_t FanControl_GL_Flag;
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};
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typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
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#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
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#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
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struct SMU7_MclkDpmScoreboard {
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uint32_t PercentageBusy;
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int32_t PIDError;
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int32_t PIDIntegral;
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int32_t PIDOutput;
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uint32_t SigmaDeltaAccum;
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uint32_t SigmaDeltaOutput;
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uint32_t SigmaDeltaLevel;
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uint32_t UtilizationSetpoint;
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uint8_t TdpClampMode;
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uint8_t TdcClampMode;
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uint8_t ThermClampMode;
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uint8_t VoltageBusy;
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int8_t CurrLevel;
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int8_t TargLevel;
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uint8_t LevelChangeInProgress;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint32_t MinimumPerfMclk;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t MclkSwitchInProgress;
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uint8_t MclkSwitchCritical;
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uint8_t IgnoreVBlank;
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uint8_t TargetMclkIndex;
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uint8_t TargetMvddIndex;
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uint8_t MclkSwitchResult;
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uint16_t VbiFailureCount;
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uint8_t VbiWaitCounter;
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uint8_t EnabledLevelsChange;
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uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
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uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
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void (*TargetStateCalculator)(uint8_t);
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void (*SavedTargetStateCalculator)(uint8_t);
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint16_t VbiTimeoutCount;
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uint16_t MclkSwitchingTime;
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uint8_t fastSwitch;
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uint8_t Save_PIC_VDDGFX_EXIT;
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uint8_t Save_PIC_VDDGFX_ENTER;
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uint8_t padding;
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};
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typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
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struct SMU7_UlvScoreboard {
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uint8_t EnterUlv;
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uint8_t ExitUlv;
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uint8_t UlvActive;
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uint8_t WaitingForUlv;
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uint8_t UlvEnable;
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uint8_t UlvRunning;
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uint8_t UlvMasterEnable;
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uint8_t padding;
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uint32_t UlvAbortedCount;
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uint32_t UlvTimeStamp;
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};
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|
|
|
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
|
|
|
|
struct VddgfxSavedRegisters {
|
|
uint32_t GPU_DBG[3];
|
|
uint32_t MEC_BaseAddress_Hi;
|
|
uint32_t MEC_BaseAddress_Lo;
|
|
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
|
|
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
|
|
uint32_t CP_INT_CNTL;
|
|
};
|
|
|
|
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
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|
|
|
struct SMU7_VddGfxScoreboard {
|
|
uint8_t VddGfxEnable;
|
|
uint8_t VddGfxActive;
|
|
uint8_t VPUResetOccured;
|
|
uint8_t padding;
|
|
|
|
uint32_t VddGfxEnteredCount;
|
|
uint32_t VddGfxAbortedCount;
|
|
|
|
uint32_t VddGfxVid;
|
|
|
|
VddgfxSavedRegisters SavedRegisters;
|
|
};
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|
|
|
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
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|
|
|
struct SMU7_TdcLimitScoreboard {
|
|
uint8_t Enable;
|
|
uint8_t Running;
|
|
uint16_t Alpha;
|
|
uint32_t FilteredIddc;
|
|
uint32_t IddcLimit;
|
|
uint32_t IddcHyst;
|
|
SMU7_HystController_Data HystControllerData;
|
|
};
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|
|
|
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
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|
|
|
struct SMU7_PkgPwrLimitScoreboard {
|
|
uint8_t Enable;
|
|
uint8_t Running;
|
|
uint16_t Alpha;
|
|
uint32_t FilteredPkgPwr;
|
|
uint32_t Limit;
|
|
uint32_t Hyst;
|
|
uint32_t LimitFromDriver;
|
|
SMU7_HystController_Data HystControllerData;
|
|
};
|
|
|
|
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
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|
|
|
struct SMU7_BapmScoreboard {
|
|
uint32_t source_powers[SMU72_DTE_SOURCES];
|
|
uint32_t source_powers_last[SMU72_DTE_SOURCES];
|
|
int32_t entity_temperatures[SMU72_NUM_GPU_TES];
|
|
int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
|
|
int32_t Limit;
|
|
int32_t Hyst;
|
|
int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
|
|
int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
|
|
uint16_t ConfigTDPPowerScalar;
|
|
uint16_t FanSpeedPowerScalar;
|
|
uint16_t OverDrivePowerScalar;
|
|
uint16_t OverDriveLimitScalar;
|
|
uint16_t FinalPowerScalar;
|
|
uint8_t VariantID;
|
|
uint8_t spare997;
|
|
|
|
SMU7_HystController_Data HystControllerData;
|
|
|
|
int32_t temperature_gradient_slope;
|
|
int32_t temperature_gradient;
|
|
uint32_t measured_temperature;
|
|
};
|
|
|
|
|
|
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
|
|
|
|
struct SMU7_AcpiScoreboard {
|
|
uint32_t SavedInterruptMask[2];
|
|
uint8_t LastACPIRequest;
|
|
uint8_t CgBifResp;
|
|
uint8_t RequestType;
|
|
uint8_t Padding;
|
|
SMU72_Discrete_ACPILevel D0Level;
|
|
};
|
|
|
|
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
|
|
|
|
struct SMU72_Discrete_PmFuses {
|
|
/* dw1 */
|
|
uint8_t SviLoadLineEn;
|
|
uint8_t SviLoadLineVddC;
|
|
uint8_t SviLoadLineTrimVddC;
|
|
uint8_t SviLoadLineOffsetVddC;
|
|
|
|
/* dw2 */
|
|
uint16_t TDC_VDDC_PkgLimit;
|
|
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
|
|
uint8_t TDC_MAWt;
|
|
|
|
/* dw3 */
|
|
uint8_t TdcWaterfallCtl;
|
|
uint8_t LPMLTemperatureMin;
|
|
uint8_t LPMLTemperatureMax;
|
|
uint8_t Reserved;
|
|
|
|
/* dw4-dw7 */
|
|
uint8_t LPMLTemperatureScaler[16];
|
|
|
|
/* dw8-dw9 */
|
|
int16_t FuzzyFan_ErrorSetDelta;
|
|
int16_t FuzzyFan_ErrorRateSetDelta;
|
|
int16_t FuzzyFan_PwmSetDelta;
|
|
uint16_t Reserved6;
|
|
|
|
/* dw10-dw14 */
|
|
uint8_t GnbLPML[16];
|
|
|
|
/* dw15 */
|
|
uint8_t GnbLPMLMaxVid;
|
|
uint8_t GnbLPMLMinVid;
|
|
uint8_t Reserved1[2];
|
|
|
|
/* dw16 */
|
|
uint16_t BapmVddCBaseLeakageHiSidd;
|
|
uint16_t BapmVddCBaseLeakageLoSidd;
|
|
};
|
|
|
|
typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
|
|
|
|
struct SMU7_Discrete_Log_Header_Table {
|
|
uint32_t version;
|
|
uint32_t asic_id;
|
|
uint16_t flags;
|
|
uint16_t entry_size;
|
|
uint32_t total_size;
|
|
uint32_t num_of_entries;
|
|
uint8_t type;
|
|
uint8_t mode;
|
|
uint8_t filler_0[2];
|
|
uint32_t filler_1[2];
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
|
|
|
|
struct SMU7_Discrete_Log_Cntl {
|
|
uint8_t Enabled;
|
|
uint8_t Type;
|
|
uint8_t padding[2];
|
|
uint32_t BufferSize;
|
|
uint32_t SamplesLogged;
|
|
uint32_t SampleSize;
|
|
uint32_t AddrL;
|
|
uint32_t AddrH;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
|
|
|
|
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
|
|
|
|
struct SMU7_Discrete_Cac_Collection_Table {
|
|
uint32_t temperature;
|
|
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
|
|
|
|
struct SMU7_Discrete_Cac_Verification_Table {
|
|
uint32_t VddcTotalPower;
|
|
uint32_t VddcLeakagePower;
|
|
uint32_t VddcConstantPower;
|
|
uint32_t VddcGfxDynamicPower;
|
|
uint32_t VddcUvdDynamicPower;
|
|
uint32_t VddcVceDynamicPower;
|
|
uint32_t VddcAcpDynamicPower;
|
|
uint32_t VddcPcieDynamicPower;
|
|
uint32_t VddcDceDynamicPower;
|
|
uint32_t VddcCurrent;
|
|
uint32_t VddcVoltage;
|
|
uint32_t VddciTotalPower;
|
|
uint32_t VddciLeakagePower;
|
|
uint32_t VddciConstantPower;
|
|
uint32_t VddciDynamicPower;
|
|
uint32_t Vddr1TotalPower;
|
|
uint32_t Vddr1LeakagePower;
|
|
uint32_t Vddr1ConstantPower;
|
|
uint32_t Vddr1DynamicPower;
|
|
uint32_t spare[4];
|
|
uint32_t temperature;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
|
|
|
|
struct SMU7_Discrete_Pm_Status_Table {
|
|
/* Thermal entities */
|
|
int32_t T_meas_max;
|
|
int32_t T_meas_acc;
|
|
int32_t T_calc_max;
|
|
int32_t T_calc_acc;
|
|
uint32_t P_scalar_acc;
|
|
uint32_t P_calc_max;
|
|
uint32_t P_calc_acc;
|
|
|
|
/*Voltage domains */
|
|
uint32_t I_calc_max;
|
|
uint32_t I_calc_acc;
|
|
uint32_t I_calc_acc_vddci;
|
|
uint32_t V_calc_noload_acc;
|
|
uint32_t V_calc_load_acc;
|
|
uint32_t V_calc_noload_acc_vddci;
|
|
uint32_t P_meas_acc;
|
|
uint32_t V_meas_noload_acc;
|
|
uint32_t V_meas_load_acc;
|
|
uint32_t I_meas_acc;
|
|
uint32_t P_meas_acc_vddci;
|
|
uint32_t V_meas_noload_acc_vddci;
|
|
uint32_t V_meas_load_acc_vddci;
|
|
uint32_t I_meas_acc_vddci;
|
|
|
|
/*Frequency */
|
|
uint16_t Sclk_dpm_residency[8];
|
|
uint16_t Uvd_dpm_residency[8];
|
|
uint16_t Vce_dpm_residency[8];
|
|
uint16_t Mclk_dpm_residency[4];
|
|
|
|
/*Chip */
|
|
uint32_t P_vddci_acc;
|
|
uint32_t P_vddr1_acc;
|
|
uint32_t P_nte1_acc;
|
|
uint32_t PkgPwr_max;
|
|
uint32_t PkgPwr_acc;
|
|
uint32_t MclkSwitchingTime_max;
|
|
uint32_t MclkSwitchingTime_acc;
|
|
uint32_t FanPwm_acc;
|
|
uint32_t FanRpm_acc;
|
|
|
|
uint32_t AccCnt;
|
|
};
|
|
|
|
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
|
|
|
|
/*FIXME THESE NEED TO BE UPDATED */
|
|
#define SMU7_SCLK_CAC 0x561
|
|
#define SMU7_MCLK_CAC 0xF9
|
|
#define SMU7_VCLK_CAC 0x2DE
|
|
#define SMU7_DCLK_CAC 0x2DE
|
|
#define SMU7_ECLK_CAC 0x25E
|
|
#define SMU7_ACLK_CAC 0x25E
|
|
#define SMU7_SAMCLK_CAC 0x25E
|
|
#define SMU7_DISPCLK_CAC 0x100
|
|
#define SMU7_CAC_CONSTANT 0x2EE3430
|
|
#define SMU7_CAC_CONSTANT_SHIFT 18
|
|
|
|
#define SMU7_VDDCI_MCLK_CONST 1765
|
|
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
|
|
#define SMU7_VDDCI_VDDCI_CONST 50958
|
|
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
|
|
#define SMU7_VDDCI_CONST 11781
|
|
|
|
#define SMU7_12C_VDDCI_MCLK_CONST 1623
|
|
#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15
|
|
#define SMU7_12C_VDDCI_VDDCI_CONST 40088
|
|
#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
|
|
#define SMU7_12C_VDDCI_CONST 20856
|
|
|
|
#define SMU7_VDDCI_STROBE_PWR 1331
|
|
|
|
#define SMU7_VDDR1_CONST 693
|
|
#define SMU7_VDDR1_CAC_WEIGHT 20
|
|
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
|
|
#define SMU7_VDDR1_STROBE_PWR 512
|
|
|
|
#define SMU7_AREA_COEFF_UVD 0xA78
|
|
#define SMU7_AREA_COEFF_VCE 0x190A
|
|
#define SMU7_AREA_COEFF_ACP 0x22D1
|
|
#define SMU7_AREA_COEFF_SAMU 0x534
|
|
|
|
/*ThermOutMode values */
|
|
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
|
|
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
|
|
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
|
|
|
|
#if !defined(SMC_MICROCODE)
|
|
#pragma pack(pop)
|
|
#endif
|
|
|
|
|
|
#endif
|
|
|