2037 lines
71 KiB
C
2037 lines
71 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/util_macros.h>
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#include "i915_reg.h"
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#include "intel_ddi.h"
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#include "intel_ddi_buf_trans.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_snps_phy.h"
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#include "intel_snps_phy_regs.h"
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/**
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* DOC: Synopsis PHY support
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*
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* Synopsis PHYs are primarily programmed by looking up magic register values
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* in tables rather than calculating the necessary values at runtime.
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*
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* Of special note is that the SNPS PHYs include a dedicated port PLL, known as
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* an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other
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* platforms and must be programming directly during the modeset sequence
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* since it is not handled by the shared DPLL framework as on other platforms.
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*/
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void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
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{
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enum phy phy;
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for_each_phy_masked(phy, ~0) {
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if (!intel_phy_is_snps(i915, phy))
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continue;
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/*
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* If calibration does not complete successfully, we'll remember
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* which phy was affected and skip setup of the corresponding
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* output later.
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*/
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if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
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DG2_PHY_DP_TX_ACK_MASK, 25))
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i915->display.snps.phy_failed_calibration |= BIT(phy);
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}
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}
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void intel_snps_phy_update_psr_power_state(struct drm_i915_private *i915,
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enum phy phy, bool enable)
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{
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u32 val;
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if (!intel_phy_is_snps(i915, phy))
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return;
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val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
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enable ? 2 : 3);
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intel_de_rmw(i915, SNPS_PHY_TX_REQ(phy),
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SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
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}
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void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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const struct intel_ddi_buf_trans *trans;
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enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
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int n_entries, ln;
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trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
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if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
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return;
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for (ln = 0; ln < 4; ln++) {
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int level = intel_ddi_level(encoder, crtc_state, ln);
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u32 val = 0;
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val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
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val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
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val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
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intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
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}
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}
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/*
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* Basic DP link rates with 100 MHz reference clock.
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*/
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static const struct intel_mpllb_state dg2_dp_rbr_100 = {
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.clock = 162000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
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};
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static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
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.clock = 270000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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};
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static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
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.clock = 540000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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};
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static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
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.clock = 810000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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};
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static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
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.clock = 1000000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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/*
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* SSC will be enabled, DP UHBR has a minimum SSC requirement.
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*/
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
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};
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static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
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.clock = 1350000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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/*
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* SSC will be enabled, DP UHBR has a minimum SSC requirement.
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*/
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
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};
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static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
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&dg2_dp_rbr_100,
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&dg2_dp_hbr1_100,
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&dg2_dp_hbr2_100,
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&dg2_dp_hbr3_100,
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&dg2_dp_uhbr10_100,
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&dg2_dp_uhbr13_100,
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NULL,
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};
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/*
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* eDP link rates with 100 MHz reference clock.
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*/
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static const struct intel_mpllb_state dg2_edp_r216 = {
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.clock = 216000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
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};
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static const struct intel_mpllb_state dg2_edp_r243 = {
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.clock = 243000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
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};
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static const struct intel_mpllb_state dg2_edp_r324 = {
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.clock = 324000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
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};
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static const struct intel_mpllb_state dg2_edp_r432 = {
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.clock = 432000,
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.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
|
|
.mpllb_sscstep =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
|
|
};
|
|
|
|
static const struct intel_mpllb_state * const dg2_edp_tables[] = {
|
|
&dg2_dp_rbr_100,
|
|
&dg2_edp_r216,
|
|
&dg2_edp_r243,
|
|
&dg2_dp_hbr1_100,
|
|
&dg2_edp_r324,
|
|
&dg2_edp_r432,
|
|
&dg2_dp_hbr2_100,
|
|
&dg2_dp_hbr3_100,
|
|
NULL,
|
|
};
|
|
|
|
/*
|
|
* HDMI link rates with 100 MHz reference clock.
|
|
*/
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_25_175 = {
|
|
.clock = 25175,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_27_0 = {
|
|
.clock = 27000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_74_25 = {
|
|
.clock = 74250,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_148_5 = {
|
|
.clock = 148500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
/* values in the below table are calculted using the algo */
|
|
static const struct intel_mpllb_state dg2_hdmi_25200 = {
|
|
.clock = 25200,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_27027 = {
|
|
.clock = 27027,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_28320 = {
|
|
.clock = 28320,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_30240 = {
|
|
.clock = 30240,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_31500 = {
|
|
.clock = 31500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_36000 = {
|
|
.clock = 36000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_40000 = {
|
|
.clock = 40000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_49500 = {
|
|
.clock = 49500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_50000 = {
|
|
.clock = 50000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_57284 = {
|
|
.clock = 57284,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_58000 = {
|
|
.clock = 58000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_65000 = {
|
|
.clock = 65000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_71000 = {
|
|
.clock = 71000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_74176 = {
|
|
.clock = 74176,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_75000 = {
|
|
.clock = 75000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_78750 = {
|
|
.clock = 78750,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_85500 = {
|
|
.clock = 85500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_88750 = {
|
|
.clock = 88750,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_106500 = {
|
|
.clock = 106500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_108000 = {
|
|
.clock = 108000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_115500 = {
|
|
.clock = 115500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_119000 = {
|
|
.clock = 119000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_135000 = {
|
|
.clock = 135000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_138500 = {
|
|
.clock = 138500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_147160 = {
|
|
.clock = 147160,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_148352 = {
|
|
.clock = 148352,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_154000 = {
|
|
.clock = 154000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_162000 = {
|
|
.clock = 162000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_209800 = {
|
|
.clock = 209800,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_262750 = {
|
|
.clock = 262750,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_267300 = {
|
|
.clock = 267300,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_268500 = {
|
|
.clock = 268500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_296703 = {
|
|
.clock = 296703,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_241500 = {
|
|
.clock = 241500,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_319890 = {
|
|
.clock = 319890,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_497750 = {
|
|
.clock = 497750,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_592000 = {
|
|
.clock = 592000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_593407 = {
|
|
.clock = 593407,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_297 = {
|
|
.clock = 297000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state dg2_hdmi_594 = {
|
|
.clock = 594000,
|
|
.ref_control =
|
|
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
|
.mpllb_cp =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
|
.mpllb_div =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
|
.mpllb_div2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
|
.mpllb_fracn1 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
|
.mpllb_fracn2 =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
|
.mpllb_sscen =
|
|
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
|
};
|
|
|
|
static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
|
|
&dg2_hdmi_25_175,
|
|
&dg2_hdmi_27_0,
|
|
&dg2_hdmi_74_25,
|
|
&dg2_hdmi_148_5,
|
|
&dg2_hdmi_297,
|
|
&dg2_hdmi_594,
|
|
&dg2_hdmi_25200,
|
|
&dg2_hdmi_27027,
|
|
&dg2_hdmi_28320,
|
|
&dg2_hdmi_30240,
|
|
&dg2_hdmi_31500,
|
|
&dg2_hdmi_36000,
|
|
&dg2_hdmi_40000,
|
|
&dg2_hdmi_49500,
|
|
&dg2_hdmi_50000,
|
|
&dg2_hdmi_57284,
|
|
&dg2_hdmi_58000,
|
|
&dg2_hdmi_65000,
|
|
&dg2_hdmi_71000,
|
|
&dg2_hdmi_74176,
|
|
&dg2_hdmi_75000,
|
|
&dg2_hdmi_78750,
|
|
&dg2_hdmi_85500,
|
|
&dg2_hdmi_88750,
|
|
&dg2_hdmi_106500,
|
|
&dg2_hdmi_108000,
|
|
&dg2_hdmi_115500,
|
|
&dg2_hdmi_119000,
|
|
&dg2_hdmi_135000,
|
|
&dg2_hdmi_138500,
|
|
&dg2_hdmi_147160,
|
|
&dg2_hdmi_148352,
|
|
&dg2_hdmi_154000,
|
|
&dg2_hdmi_162000,
|
|
&dg2_hdmi_209800,
|
|
&dg2_hdmi_241500,
|
|
&dg2_hdmi_262750,
|
|
&dg2_hdmi_267300,
|
|
&dg2_hdmi_268500,
|
|
&dg2_hdmi_296703,
|
|
&dg2_hdmi_319890,
|
|
&dg2_hdmi_497750,
|
|
&dg2_hdmi_592000,
|
|
&dg2_hdmi_593407,
|
|
NULL,
|
|
};
|
|
|
|
static const struct intel_mpllb_state * const *
|
|
intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
|
|
struct intel_encoder *encoder)
|
|
{
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
|
|
return dg2_edp_tables;
|
|
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
|
|
return dg2_dp_100_tables;
|
|
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
|
return dg2_hdmi_tables;
|
|
}
|
|
|
|
MISSING_CASE(encoder->type);
|
|
return NULL;
|
|
}
|
|
|
|
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
|
|
struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
const struct intel_mpllb_state * const *tables;
|
|
int i;
|
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
|
if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
|
|
!= MODE_OK) {
|
|
/*
|
|
* FIXME: Can only support fixed HDMI frequencies
|
|
* until we have a proper algorithm under a valid
|
|
* license.
|
|
*/
|
|
drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
|
|
crtc_state->port_clock);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
tables = intel_mpllb_tables_get(crtc_state, encoder);
|
|
if (!tables)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; tables[i]; i++) {
|
|
if (crtc_state->port_clock == tables[i]->clock) {
|
|
crtc_state->mpllb_state = *tables[i];
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
void intel_mpllb_enable(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state;
|
|
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
|
i915_reg_t enable_reg = (phy <= PHY_D ?
|
|
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
|
|
|
|
/*
|
|
* 3. Software programs the following PLL registers for the desired
|
|
* frequency.
|
|
*/
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
|
|
|
|
/*
|
|
* 4. If the frequency will result in a change to the voltage
|
|
* requirement, follow the Display Voltage Frequency Switching -
|
|
* Sequence Before Frequency Change.
|
|
*
|
|
* We handle this step in bxt_set_cdclk().
|
|
*/
|
|
|
|
/* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
|
|
intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE);
|
|
|
|
/*
|
|
* 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
|
|
* will keep the PLL running during the DDI lane programming and any
|
|
* typeC DP cable disconnect. Do not set the force before enabling the
|
|
* PLL because that will start the PLL before it has sampled the
|
|
* divider values.
|
|
*/
|
|
intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
|
|
pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
|
|
|
|
/*
|
|
* 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
|
|
* is locked at new settings. This register bit is sampling PHY
|
|
* dp_mpllb_state interface signal.
|
|
*/
|
|
if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
|
|
drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
|
|
|
|
/*
|
|
* 11. If the frequency will result in a change to the voltage
|
|
* requirement, follow the Display Voltage Frequency Switching -
|
|
* Sequence After Frequency Change.
|
|
*
|
|
* We handle this step in bxt_set_cdclk().
|
|
*/
|
|
}
|
|
|
|
void intel_mpllb_disable(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
i915_reg_t enable_reg = (phy <= PHY_D ?
|
|
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
|
|
|
|
/*
|
|
* 1. If the frequency will result in a change to the voltage
|
|
* requirement, follow the Display Voltage Frequency Switching -
|
|
* Sequence Before Frequency Change.
|
|
*
|
|
* We handle this step in bxt_set_cdclk().
|
|
*/
|
|
|
|
/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
|
|
intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
|
|
|
|
/*
|
|
* 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
|
|
* This will allow the PLL to stop running.
|
|
*/
|
|
intel_de_rmw(i915, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);
|
|
|
|
/*
|
|
* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
|
|
* (dp_txX_ack) that the new transmitter setting request is completed.
|
|
*/
|
|
if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
|
|
drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
|
|
|
|
/*
|
|
* 6. If the frequency will result in a change to the voltage
|
|
* requirement, follow the Display Voltage Frequency Switching -
|
|
* Sequence After Frequency Change.
|
|
*
|
|
* We handle this step in bxt_set_cdclk().
|
|
*/
|
|
}
|
|
|
|
int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
|
|
const struct intel_mpllb_state *pll_state)
|
|
{
|
|
unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
|
|
unsigned int multiplier, tx_clk_div, refclk;
|
|
bool frac_en;
|
|
|
|
if (0)
|
|
refclk = 38400;
|
|
else
|
|
refclk = 100000;
|
|
|
|
refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
|
|
|
|
frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
|
|
|
|
if (frac_en) {
|
|
frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
|
|
frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
|
|
frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
|
|
}
|
|
|
|
multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
|
|
|
|
tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
|
|
|
|
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
|
|
DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
|
|
10 << (tx_clk_div + 16));
|
|
}
|
|
|
|
void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
|
|
struct intel_mpllb_state *pll_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
|
|
|
pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy));
|
|
pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy));
|
|
pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy));
|
|
pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy));
|
|
pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy));
|
|
pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy));
|
|
pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy));
|
|
|
|
/*
|
|
* REF_CONTROL is under firmware control and never programmed by the
|
|
* driver; we read it only for sanity checking purposes. The bspec
|
|
* only tells us the expected value for one field in this register,
|
|
* so we'll only read out those specific bits here.
|
|
*/
|
|
pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) &
|
|
SNPS_PHY_REF_CONTROL_REF_RANGE;
|
|
|
|
/*
|
|
* MPLLB_DIV is programmed twice, once with the software-computed
|
|
* state, then again with the MPLLB_FORCE_EN bit added. Drop that
|
|
* extra bit during readout so that we return the actual expected
|
|
* software state.
|
|
*/
|
|
pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
|
|
}
|
|
|
|
int intel_snps_phy_check_hdmi_link_rate(int clock)
|
|
{
|
|
const struct intel_mpllb_state * const *tables = dg2_hdmi_tables;
|
|
int i;
|
|
|
|
for (i = 0; tables[i]; i++) {
|
|
if (clock == tables[i]->clock)
|
|
return MODE_OK;
|
|
}
|
|
|
|
return MODE_CLOCK_RANGE;
|
|
}
|
|
|
|
void intel_mpllb_state_verify(struct intel_atomic_state *state,
|
|
struct intel_crtc_state *new_crtc_state)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(state->base.dev);
|
|
struct intel_mpllb_state mpllb_hw_state = { 0 };
|
|
struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
|
|
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
|
|
struct intel_encoder *encoder;
|
|
|
|
if (!IS_DG2(i915))
|
|
return;
|
|
|
|
if (!new_crtc_state->hw.active)
|
|
return;
|
|
|
|
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
|
|
intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
|
|
|
|
#define MPLLB_CHECK(__name) \
|
|
I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name, \
|
|
"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
|
|
crtc->base.base.id, crtc->base.name, \
|
|
__stringify(__name), \
|
|
mpllb_sw_state->__name, mpllb_hw_state.__name)
|
|
|
|
MPLLB_CHECK(mpllb_cp);
|
|
MPLLB_CHECK(mpllb_div);
|
|
MPLLB_CHECK(mpllb_div2);
|
|
MPLLB_CHECK(mpllb_fracn1);
|
|
MPLLB_CHECK(mpllb_fracn2);
|
|
MPLLB_CHECK(mpllb_sscen);
|
|
MPLLB_CHECK(mpllb_sscstep);
|
|
|
|
/*
|
|
* ref_control is handled by the hardware/firemware and never
|
|
* programmed by the software, but the proper values are supplied
|
|
* in the bspec for verification purposes.
|
|
*/
|
|
MPLLB_CHECK(ref_control);
|
|
|
|
#undef MPLLB_CHECK
|
|
}
|