241 lines
6.5 KiB
C
241 lines
6.5 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_gt.h"
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#include "intel_gt_clock_utils.h"
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#include "intel_gt_print.h"
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#include "intel_gt_regs.h"
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static u32 read_reference_ts_freq(struct intel_uncore *uncore)
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{
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u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE);
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u32 base_freq, frac_freq;
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base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
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GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
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base_freq *= 1000000;
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frac_freq = ((ts_override &
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GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
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GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
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frac_freq = 1000000 / (frac_freq + 1);
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return base_freq + frac_freq;
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}
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static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
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u32 rpm_config_reg)
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{
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u32 f19_2_mhz = 19200000;
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u32 f24_mhz = 24000000;
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u32 f25_mhz = 25000000;
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u32 f38_4_mhz = 38400000;
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u32 crystal_clock =
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(rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
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GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
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switch (crystal_clock) {
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
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return f24_mhz;
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
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return f19_2_mhz;
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
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return f38_4_mhz;
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
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return f25_mhz;
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default:
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MISSING_CASE(crystal_clock);
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return 0;
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}
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}
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static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
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{
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u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
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u32 freq = 0;
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/*
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* Note that on gen11+, the clock frequency may be reconfigured.
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* We do not, and we assume nobody else does.
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*
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* First figure out the reference frequency. There are 2 ways
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* we can compute the frequency, either through the
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* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
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* tells us which one we should use.
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*/
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if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
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freq = read_reference_ts_freq(uncore);
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} else {
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u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
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freq = gen11_get_crystal_clock_freq(uncore, c0);
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/*
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* Now figure out how the command stream's timestamp
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* register increments from this frequency (it might
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* increment only every few clock cycle).
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*/
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freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
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GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
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}
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return freq;
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}
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static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
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{
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u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
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u32 freq = 0;
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if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
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freq = read_reference_ts_freq(uncore);
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} else {
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freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000;
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/*
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* Now figure out how the command stream's timestamp
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* register increments from this frequency (it might
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* increment only every few clock cycle).
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*/
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freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
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CTC_SHIFT_PARAMETER_SHIFT);
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}
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return freq;
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}
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static u32 gen6_read_clock_frequency(struct intel_uncore *uncore)
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{
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/*
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* PRMs say:
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*
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* "The PCU TSC counts 10ns increments; this timestamp
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* reflects bits 38:3 of the TSC (i.e. 80ns granularity,
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* rolling over every 1.5 hours).
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*/
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return 12500000;
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}
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static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
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{
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/*
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* 63:32 increments every 1000 ns
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* 31:0 mbz
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*/
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return 1000000000 / 1000;
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}
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static u32 g4x_read_clock_frequency(struct intel_uncore *uncore)
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{
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/*
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* 63:20 increments every 1/4 ns
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* 19:0 mbz
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*
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* -> 63:32 increments every 1024 ns
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*/
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return 1000000000 / 1024;
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}
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static u32 gen4_read_clock_frequency(struct intel_uncore *uncore)
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{
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/*
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* PRMs say:
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*
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* "The value in this register increments once every 16
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* hclks." (through the “Clocking Configuration”
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* (“CLKCFG”) MCHBAR register)
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*
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* Testing on actual hardware has shown there is no /16.
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*/
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return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
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}
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static u32 read_clock_frequency(struct intel_uncore *uncore)
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{
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if (GRAPHICS_VER(uncore->i915) >= 11)
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return gen11_read_clock_frequency(uncore);
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else if (GRAPHICS_VER(uncore->i915) >= 9)
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return gen9_read_clock_frequency(uncore);
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else if (GRAPHICS_VER(uncore->i915) >= 6)
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return gen6_read_clock_frequency(uncore);
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else if (GRAPHICS_VER(uncore->i915) == 5)
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return gen5_read_clock_frequency(uncore);
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else if (IS_G4X(uncore->i915))
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return g4x_read_clock_frequency(uncore);
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else if (GRAPHICS_VER(uncore->i915) == 4)
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return gen4_read_clock_frequency(uncore);
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else
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return 0;
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}
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void intel_gt_init_clock_frequency(struct intel_gt *gt)
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{
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gt->clock_frequency = read_clock_frequency(gt->uncore);
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/* Icelake appears to use another fixed frequency for CTX_TIMESTAMP */
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if (GRAPHICS_VER(gt->i915) == 11)
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gt->clock_period_ns = NSEC_PER_SEC / 13750000;
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else if (gt->clock_frequency)
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gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
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GT_TRACE(gt,
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"Using clock frequency: %dkHz, period: %dns, wrap: %lldms\n",
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gt->clock_frequency / 1000,
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gt->clock_period_ns,
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div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX),
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USEC_PER_SEC));
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}
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
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void intel_gt_check_clock_frequency(const struct intel_gt *gt)
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{
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if (gt->clock_frequency != read_clock_frequency(gt->uncore)) {
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gt_err(gt, "GT clock frequency changed, was %uHz, now %uHz!\n",
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gt->clock_frequency,
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read_clock_frequency(gt->uncore));
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}
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}
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#endif
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static u64 div_u64_roundup(u64 nom, u32 den)
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{
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return div_u64(nom + den - 1, den);
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}
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u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count)
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{
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return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency);
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}
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u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count)
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{
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return intel_gt_clock_interval_to_ns(gt, 16 * count);
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}
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u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns)
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{
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return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC);
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}
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u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
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{
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u64 val;
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/*
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* Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
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* 8300) freezing up around GPU hangs. Looks as if even
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* scheduling/timer interrupts start misbehaving if the RPS
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* EI/thresholds are "bad", leading to a very sluggish or even
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* frozen machine.
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*/
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val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
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if (GRAPHICS_VER(gt->i915) == 6)
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val = div_u64_roundup(val, 25) * 25;
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return val;
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}
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