526 lines
15 KiB
C
526 lines
15 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014-2019 Intel Corporation
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*/
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#ifndef _INTEL_GUC_FWIF_H
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#define _INTEL_GUC_FWIF_H
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#include <linux/bits.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include "gt/intel_engine_types.h"
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#include "abi/guc_actions_abi.h"
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#include "abi/guc_actions_slpc_abi.h"
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#include "abi/guc_errors_abi.h"
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#include "abi/guc_communication_mmio_abi.h"
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#include "abi/guc_communication_ctb_abi.h"
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#include "abi/guc_klvs_abi.h"
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#include "abi/guc_messages_abi.h"
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/* Payload length only i.e. don't include G2H header length */
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#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2
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#define G2H_LEN_DW_DEREGISTER_CONTEXT 1
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#define GUC_CONTEXT_DISABLE 0
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#define GUC_CONTEXT_ENABLE 1
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#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
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#define GUC_CLIENT_PRIORITY_HIGH 1
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#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
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#define GUC_CLIENT_PRIORITY_NORMAL 3
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#define GUC_CLIENT_PRIORITY_NUM 4
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#define GUC_MAX_CONTEXT_ID 65535
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#define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
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#define GUC_RENDER_ENGINE 0
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#define GUC_VIDEO_ENGINE 1
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#define GUC_BLITTER_ENGINE 2
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#define GUC_VIDEOENHANCE_ENGINE 3
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#define GUC_VIDEO_ENGINE2 4
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#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
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#define GUC_RENDER_CLASS 0
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#define GUC_VIDEO_CLASS 1
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#define GUC_VIDEOENHANCE_CLASS 2
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#define GUC_BLITTER_CLASS 3
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#define GUC_COMPUTE_CLASS 4
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#define GUC_GSC_OTHER_CLASS 5
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#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
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#define GUC_MAX_ENGINE_CLASSES 16
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#define GUC_MAX_INSTANCES_PER_CLASS 32
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#define GUC_DOORBELL_INVALID 256
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/*
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* Work queue item header definitions
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*
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* Work queue is circular buffer used to submit complex (multi-lrc) submissions
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* to the GuC. A work queue item is an entry in the circular buffer.
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*/
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#define WQ_STATUS_ACTIVE 1
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#define WQ_STATUS_SUSPENDED 2
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#define WQ_STATUS_CMD_ERROR 3
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#define WQ_STATUS_ENGINE_ID_NOT_USED 4
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#define WQ_STATUS_SUSPENDED_FROM_RESET 5
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#define WQ_TYPE_BATCH_BUF 0x1
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#define WQ_TYPE_PSEUDO 0x2
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#define WQ_TYPE_INORDER 0x3
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#define WQ_TYPE_NOOP 0x4
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#define WQ_TYPE_MULTI_LRC 0x5
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#define WQ_TYPE_MASK GENMASK(7, 0)
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#define WQ_LEN_MASK GENMASK(26, 16)
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#define WQ_GUC_ID_MASK GENMASK(15, 0)
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#define WQ_RING_TAIL_MASK GENMASK(28, 18)
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#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
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#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
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#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
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#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
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#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
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#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
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#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
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#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
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#define GUC_CTL_LOG_PARAMS 0
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#define GUC_LOG_VALID BIT(0)
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#define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
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#define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
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#define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
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#define GUC_LOG_CRASH_SHIFT 4
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#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
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#define GUC_LOG_DEBUG_SHIFT 6
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#define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
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#define GUC_LOG_CAPTURE_SHIFT 10
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#define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT)
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#define GUC_LOG_BUF_ADDR_SHIFT 12
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#define GUC_CTL_WA 1
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#define GUC_WA_GAM_CREDITS BIT(10)
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#define GUC_WA_DUAL_QUEUE BIT(11)
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#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
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#define GUC_WA_CONTEXT_ISOLATION BIT(15)
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#define GUC_WA_PRE_PARSER BIT(14)
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#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
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#define GUC_WA_POLLCS BIT(18)
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#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
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#define GUC_CTL_FEATURE 2
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#define GUC_CTL_ENABLE_SLPC BIT(2)
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#define GUC_CTL_DISABLE_SCHEDULER BIT(14)
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#define GUC_CTL_DEBUG 3
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#define GUC_LOG_VERBOSITY_SHIFT 0
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#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
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/* Verbosity range-check limits, without the shift */
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#define GUC_LOG_VERBOSITY_MIN 0
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#define GUC_LOG_VERBOSITY_MAX 3
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#define GUC_LOG_VERBOSITY_MASK 0x0000000f
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#define GUC_LOG_DESTINATION_MASK (3 << 4)
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#define GUC_LOG_DISABLED (1 << 6)
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#define GUC_PROFILE_ENABLED (1 << 7)
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#define GUC_CTL_ADS 4
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#define GUC_ADS_ADDR_SHIFT 1
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#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
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#define GUC_CTL_DEVID 5
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#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
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/* Generic GT SysInfo data types */
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#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
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#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
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#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
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#define GUC_GENERIC_GT_SYSINFO_MAX 16
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/*
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* The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6].
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* Bit 7 can be used for operations that apply to all engine classes&instances.
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*/
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#define GUC_ENGINE_CLASS_SHIFT 0
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#define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT)
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#define GUC_ENGINE_INSTANCE_SHIFT 3
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#define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT)
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#define GUC_ENGINE_ALL_INSTANCES BIT(7)
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#define MAKE_GUC_ID(class, instance) \
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(((class) << GUC_ENGINE_CLASS_SHIFT) | \
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((instance) << GUC_ENGINE_INSTANCE_SHIFT))
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#define GUC_ID_TO_ENGINE_CLASS(guc_id) \
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(((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT)
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#define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
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(((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
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#define SLPC_EVENT(id, c) (\
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FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
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FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \
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)
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/* the GuC arrays don't include OTHER_CLASS */
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static u8 engine_class_guc_class_map[] = {
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[RENDER_CLASS] = GUC_RENDER_CLASS,
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[COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS,
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[VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS,
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[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
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[OTHER_CLASS] = GUC_GSC_OTHER_CLASS,
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[COMPUTE_CLASS] = GUC_COMPUTE_CLASS,
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};
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static u8 guc_class_engine_class_map[] = {
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[GUC_RENDER_CLASS] = RENDER_CLASS,
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[GUC_BLITTER_CLASS] = COPY_ENGINE_CLASS,
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[GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS,
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[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
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[GUC_COMPUTE_CLASS] = COMPUTE_CLASS,
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[GUC_GSC_OTHER_CLASS] = OTHER_CLASS,
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};
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static inline u8 engine_class_to_guc_class(u8 class)
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{
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BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
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GEM_BUG_ON(class > MAX_ENGINE_CLASS);
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return engine_class_guc_class_map[class];
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}
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static inline u8 guc_class_to_engine_class(u8 guc_class)
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{
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BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1);
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GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
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return guc_class_engine_class_map[guc_class];
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}
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/* Work item for submitting workloads into work queue of GuC. */
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struct guc_wq_item {
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u32 header;
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u32 context_desc;
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u32 submit_element_info;
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u32 fence_id;
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} __packed;
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struct guc_process_desc_v69 {
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u32 stage_id;
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u64 db_base_addr;
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u32 head;
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u32 tail;
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u32 error_offset;
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u64 wq_base_addr;
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u32 wq_size_bytes;
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u32 wq_status;
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u32 engine_presence;
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u32 priority;
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u32 reserved[36];
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} __packed;
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struct guc_sched_wq_desc {
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u32 head;
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u32 tail;
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u32 error_offset;
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u32 wq_status;
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u32 reserved[28];
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} __packed;
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/* Helper for context registration H2G */
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struct guc_ctxt_registration_info {
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u32 flags;
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u32 context_idx;
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u32 engine_class;
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u32 engine_submit_mask;
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u32 wq_desc_lo;
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u32 wq_desc_hi;
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u32 wq_base_lo;
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u32 wq_base_hi;
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u32 wq_size;
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u32 hwlrca_lo;
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u32 hwlrca_hi;
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};
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#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
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/* Preempt to idle on quantum expiry */
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#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE_V69 BIT(0)
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/*
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* GuC Context registration descriptor.
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* FIXME: This is only required to exist during context registration.
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* The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
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* is not required.
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*/
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struct guc_lrc_desc_v69 {
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u32 hw_context_desc;
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u32 slpm_perf_mode_hint; /* SPLC v1 only */
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u32 slpm_freq_hint;
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u32 engine_submit_mask; /* In logical space */
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u8 engine_class;
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u8 reserved0[3];
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u32 priority;
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u32 process_desc;
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u32 wq_addr;
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u32 wq_size;
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u32 context_flags; /* CONTEXT_REGISTRATION_* */
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/* Time for one workload to execute. (in micro seconds) */
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u32 execution_quantum;
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/* Time to wait for a preemption request to complete before issuing a
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* reset. (in micro seconds).
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*/
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u32 preemption_timeout;
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u32 policy_flags; /* CONTEXT_POLICY_* */
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u32 reserved1[19];
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} __packed;
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/* 32-bit KLV structure as used by policy updates and others */
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struct guc_klv_generic_dw_t {
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u32 kl;
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u32 value;
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} __packed;
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/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
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struct guc_update_context_policy_header {
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u32 action;
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u32 ctx_id;
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} __packed;
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struct guc_update_context_policy {
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struct guc_update_context_policy_header header;
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struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
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} __packed;
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/* Format of the UPDATE_SCHEDULING_POLICIES H2G data packet */
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struct guc_update_scheduling_policy_header {
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u32 action;
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} __packed;
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/*
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* Can't dynmically allocate memory for the scheduling policy KLV because
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* it will be sent from within the reset path. Need a fixed size lump on
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* the stack instead :(.
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*
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* Currently, there is only one KLV defined, which has 1 word of KL + 2 words of V.
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*/
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#define MAX_SCHEDULING_POLICY_SIZE 3
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struct guc_update_scheduling_policy {
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struct guc_update_scheduling_policy_header header;
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u32 data[MAX_SCHEDULING_POLICY_SIZE];
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} __packed;
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#define GUC_POWER_UNSPECIFIED 0
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#define GUC_POWER_D0 1
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#define GUC_POWER_D1 2
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#define GUC_POWER_D2 3
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#define GUC_POWER_D3 4
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/* Scheduling policy settings */
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#define GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION 100 /* in ms */
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#define GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO 50 /* in percent */
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#define GLOBAL_POLICY_MAX_NUM_WI 15
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/* Don't reset an engine upon preemption failure */
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#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
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#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
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/*
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* GuC converts the timeout to clock ticks internally. Different platforms have
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* different GuC clocks. Thus, the maximum value before overflow is platform
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* dependent. Current worst case scenario is about 110s. So, the spec says to
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* limit to 100s to be safe.
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*/
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#define GUC_POLICY_MAX_EXEC_QUANTUM_US (100 * 1000 * 1000UL)
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#define GUC_POLICY_MAX_PREEMPT_TIMEOUT_US (100 * 1000 * 1000UL)
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static inline u32 guc_policy_max_exec_quantum_ms(void)
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{
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BUILD_BUG_ON(GUC_POLICY_MAX_EXEC_QUANTUM_US >= UINT_MAX);
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return GUC_POLICY_MAX_EXEC_QUANTUM_US / 1000;
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}
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static inline u32 guc_policy_max_preempt_timeout_ms(void)
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{
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BUILD_BUG_ON(GUC_POLICY_MAX_PREEMPT_TIMEOUT_US >= UINT_MAX);
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return GUC_POLICY_MAX_PREEMPT_TIMEOUT_US / 1000;
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}
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struct guc_policies {
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u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
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/* In micro seconds. How much time to allow before DPC processing is
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* called back via interrupt (to prevent DPC queue drain starving).
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* Typically 1000s of micro seconds (example only, not granularity). */
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u32 dpc_promote_time;
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/* Must be set to take these new values. */
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u32 is_valid;
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/* Max number of WIs to process per call. A large value may keep CS
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* idle. */
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u32 max_num_work_items;
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u32 global_flags;
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u32 reserved[4];
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} __packed;
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/* GuC MMIO reg state struct */
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struct guc_mmio_reg {
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u32 offset;
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u32 value;
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u32 flags;
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#define GUC_REGSET_MASKED BIT(0)
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#define GUC_REGSET_NEEDS_STEERING BIT(1)
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#define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
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#define GUC_REGSET_RESTORE_ONLY BIT(3)
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#define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)
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#define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)
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u32 mask;
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} __packed;
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/* GuC register sets */
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struct guc_mmio_reg_set {
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u32 address;
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u16 count;
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u16 reserved;
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} __packed;
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/* HW info */
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struct guc_gt_system_info {
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u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
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u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
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} __packed;
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enum {
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GUC_CAPTURE_LIST_INDEX_PF = 0,
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GUC_CAPTURE_LIST_INDEX_VF = 1,
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GUC_CAPTURE_LIST_INDEX_MAX = 2,
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};
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/*Register-types of GuC capture register lists */
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enum guc_capture_type {
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GUC_CAPTURE_LIST_TYPE_GLOBAL = 0,
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GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
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GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
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GUC_CAPTURE_LIST_TYPE_MAX,
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};
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/* GuC Additional Data Struct */
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struct guc_ads {
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struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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u32 reserved0;
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u32 scheduler_policies;
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u32 gt_system_info;
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u32 reserved1;
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u32 control_data;
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u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
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u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
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u32 private_data;
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u32 reserved2;
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u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
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u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
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u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
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u32 reserved[14];
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} __packed;
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/* Engine usage stats */
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struct guc_engine_usage_record {
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u32 current_context_index;
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u32 last_switch_in_stamp;
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u32 reserved0;
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u32 total_runtime;
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u32 reserved1[4];
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} __packed;
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|
|
struct guc_engine_usage {
|
|
struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
|
|
} __packed;
|
|
|
|
/* GuC logging structures */
|
|
|
|
enum guc_log_buffer_type {
|
|
GUC_DEBUG_LOG_BUFFER,
|
|
GUC_CRASH_DUMP_LOG_BUFFER,
|
|
GUC_CAPTURE_LOG_BUFFER,
|
|
GUC_MAX_LOG_BUFFER
|
|
};
|
|
|
|
/**
|
|
* struct guc_log_buffer_state - GuC log buffer state
|
|
*
|
|
* Below state structure is used for coordination of retrieval of GuC firmware
|
|
* logs. Separate state is maintained for each log buffer type.
|
|
* read_ptr points to the location where i915 read last in log buffer and
|
|
* is read only for GuC firmware. write_ptr is incremented by GuC with number
|
|
* of bytes written for each log entry and is read only for i915.
|
|
* When any type of log buffer becomes half full, GuC sends a flush interrupt.
|
|
* GuC firmware expects that while it is writing to 2nd half of the buffer,
|
|
* first half would get consumed by Host and then get a flush completed
|
|
* acknowledgment from Host, so that it does not end up doing any overwrite
|
|
* causing loss of logs. So when buffer gets half filled & i915 has requested
|
|
* for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
|
|
* to the value of write_ptr and raise the interrupt.
|
|
* On receiving the interrupt i915 should read the buffer, clear flush_to_file
|
|
* field and also update read_ptr with the value of sample_write_ptr, before
|
|
* sending an acknowledgment to GuC. marker & version fields are for internal
|
|
* usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
|
|
* time GuC detects the log buffer overflow.
|
|
*/
|
|
struct guc_log_buffer_state {
|
|
u32 marker[2];
|
|
u32 read_ptr;
|
|
u32 write_ptr;
|
|
u32 size;
|
|
u32 sampled_write_ptr;
|
|
u32 wrap_offset;
|
|
union {
|
|
struct {
|
|
u32 flush_to_file:1;
|
|
u32 buffer_full_cnt:4;
|
|
u32 reserved:27;
|
|
};
|
|
u32 flags;
|
|
};
|
|
u32 version;
|
|
} __packed;
|
|
|
|
struct guc_ctx_report {
|
|
u32 report_return_status;
|
|
u32 reserved1[64];
|
|
u32 affected_count;
|
|
u32 reserved2[2];
|
|
} __packed;
|
|
|
|
/* GuC Shared Context Data Struct */
|
|
struct guc_shared_ctx_data {
|
|
u32 addr_of_last_preempted_data_low;
|
|
u32 addr_of_last_preempted_data_high;
|
|
u32 addr_of_last_preempted_data_high_tmp;
|
|
u32 padding;
|
|
u32 is_mapped_to_proxy;
|
|
u32 proxy_ctx_id;
|
|
u32 engine_reset_ctx_id;
|
|
u32 media_reset_count;
|
|
u32 reserved1[8];
|
|
u32 uk_last_ctx_switch_reason;
|
|
u32 was_reset;
|
|
u32 lrca_gpu_addr;
|
|
u64 execlist_ctx;
|
|
u32 reserved2[66];
|
|
struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
|
|
} __packed;
|
|
|
|
/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
|
|
enum intel_guc_recv_message {
|
|
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
|
|
INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30),
|
|
};
|
|
|
|
#endif
|