481 lines
14 KiB
C
481 lines
14 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/string_helpers.h>
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#include <linux/kernel.h>
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#include <drm/drm_print.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "i915_trace.h"
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#include "i915_utils.h"
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#include "intel_pm.h"
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#include "vlv_suspend.h"
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#include "gt/intel_gt_regs.h"
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struct vlv_s0ix_state {
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/* GAM */
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u32 wr_watermark;
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u32 gfx_prio_ctrl;
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u32 arb_mode;
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u32 gfx_pend_tlb0;
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u32 gfx_pend_tlb1;
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u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
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u32 media_max_req_count;
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u32 gfx_max_req_count;
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u32 render_hwsp;
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u32 ecochk;
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u32 bsd_hwsp;
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u32 blt_hwsp;
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u32 tlb_rd_addr;
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/* MBC */
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u32 g3dctl;
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u32 gsckgctl;
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u32 mbctl;
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/* GCP */
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u32 ucgctl1;
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u32 ucgctl3;
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u32 rcgctl1;
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u32 rcgctl2;
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u32 rstctl;
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u32 misccpctl;
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/* GPM */
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u32 gfxpause;
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u32 rpdeuhwtc;
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u32 rpdeuc;
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u32 ecobus;
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u32 pwrdwnupctl;
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u32 rp_down_timeout;
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u32 rp_deucsw;
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u32 rcubmabdtmr;
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u32 rcedata;
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u32 spare2gh;
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/* Display 1 CZ domain */
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u32 gt_imr;
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u32 gt_ier;
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u32 pm_imr;
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u32 pm_ier;
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u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
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/* GT SA CZ domain */
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u32 tilectl;
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u32 gt_fifoctl;
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u32 gtlc_wake_ctrl;
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u32 gtlc_survive;
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u32 pmwgicz;
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/* Display 2 CZ domain */
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u32 gu_ctl0;
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u32 gu_ctl1;
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u32 pcbr;
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u32 clock_gate_dis2;
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};
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/*
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* Save all Gunit registers that may be lost after a D3 and a subsequent
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* S0i[R123] transition. The list of registers needing a save/restore is
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* defined in the VLV2_S0IXRegs document. This documents marks all Gunit
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* registers in the following way:
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* - Driver: saved/restored by the driver
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* - Punit : saved/restored by the Punit firmware
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* - No, w/o marking: no need to save/restore, since the register is R/O or
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* used internally by the HW in a way that doesn't depend
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* keeping the content across a suspend/resume.
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* - Debug : used for debugging
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*
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* We save/restore all registers marked with 'Driver', with the following
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* exceptions:
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* - Registers out of use, including also registers marked with 'Debug'.
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* These have no effect on the driver's operation, so we don't save/restore
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* them to reduce the overhead.
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* - Registers that are fully setup by an initialization function called from
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* the resume path. For example many clock gating and RPS/RC6 registers.
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* - Registers that provide the right functionality with their reset defaults.
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*
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* TODO: Except for registers that based on the above 3 criteria can be safely
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* ignored, we save/restore all others, practically treating the HW context as
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* a black-box for the driver. Further investigation is needed to reduce the
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* saved/restored registers even further, by following the same 3 criteria.
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*/
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static void vlv_save_gunit_s0ix_state(struct drm_i915_private *i915)
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{
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struct vlv_s0ix_state *s = i915->vlv_s0ix_state;
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struct intel_uncore *uncore = &i915->uncore;
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int i;
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if (!s)
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return;
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/* GAM 0x4000-0x4770 */
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s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK);
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s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL);
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s->arb_mode = intel_uncore_read(uncore, ARB_MODE);
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s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0);
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s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1);
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for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
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s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i));
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s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT);
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s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT);
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s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7);
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s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
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s->bsd_hwsp = intel_uncore_read(uncore, BSD_HWS_PGA_GEN7);
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s->blt_hwsp = intel_uncore_read(uncore, BLT_HWS_PGA_GEN7);
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s->tlb_rd_addr = intel_uncore_read(uncore, GEN7_TLB_RD_ADDR);
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/* MBC 0x9024-0x91D0, 0x8500 */
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s->g3dctl = intel_uncore_read(uncore, VLV_G3DCTL);
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s->gsckgctl = intel_uncore_read(uncore, VLV_GSCKGCTL);
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s->mbctl = intel_uncore_read(uncore, GEN6_MBCTL);
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/* GCP 0x9400-0x9424, 0x8100-0x810C */
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s->ucgctl1 = intel_uncore_read(uncore, GEN6_UCGCTL1);
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s->ucgctl3 = intel_uncore_read(uncore, GEN6_UCGCTL3);
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s->rcgctl1 = intel_uncore_read(uncore, GEN6_RCGCTL1);
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s->rcgctl2 = intel_uncore_read(uncore, GEN6_RCGCTL2);
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s->rstctl = intel_uncore_read(uncore, GEN6_RSTCTL);
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s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL);
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/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
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s->gfxpause = intel_uncore_read(uncore, GEN6_GFXPAUSE);
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s->rpdeuhwtc = intel_uncore_read(uncore, GEN6_RPDEUHWTC);
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s->rpdeuc = intel_uncore_read(uncore, GEN6_RPDEUC);
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s->ecobus = intel_uncore_read(uncore, ECOBUS);
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s->pwrdwnupctl = intel_uncore_read(uncore, VLV_PWRDWNUPCTL);
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s->rp_down_timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_TIMEOUT);
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s->rp_deucsw = intel_uncore_read(uncore, GEN6_RPDEUCSW);
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s->rcubmabdtmr = intel_uncore_read(uncore, GEN6_RCUBMABDTMR);
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s->rcedata = intel_uncore_read(uncore, VLV_RCEDATA);
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s->spare2gh = intel_uncore_read(uncore, VLV_SPAREG2H);
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/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
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s->gt_imr = intel_uncore_read(uncore, GTIMR);
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s->gt_ier = intel_uncore_read(uncore, GTIER);
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s->pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
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s->pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
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for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
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s->gt_scratch[i] = intel_uncore_read(uncore, GEN7_GT_SCRATCH(i));
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/* GT SA CZ domain, 0x100000-0x138124 */
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s->tilectl = intel_uncore_read(uncore, TILECTL);
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s->gt_fifoctl = intel_uncore_read(uncore, GTFIFOCTL);
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s->gtlc_wake_ctrl = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL);
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s->gtlc_survive = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG);
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s->pmwgicz = intel_uncore_read(uncore, VLV_PMWGICZ);
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/* Gunit-Display CZ domain, 0x182028-0x1821CF */
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s->gu_ctl0 = intel_uncore_read(uncore, VLV_GU_CTL0);
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s->gu_ctl1 = intel_uncore_read(uncore, VLV_GU_CTL1);
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s->pcbr = intel_uncore_read(uncore, VLV_PCBR);
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s->clock_gate_dis2 = intel_uncore_read(uncore, VLV_GUNIT_CLOCK_GATE2);
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/*
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* Not saving any of:
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* DFT, 0x9800-0x9EC0
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* SARB, 0xB000-0xB1FC
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* GAC, 0x5208-0x524C, 0x14000-0x14C000
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* PCI CFG
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*/
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}
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static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *i915)
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{
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struct vlv_s0ix_state *s = i915->vlv_s0ix_state;
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struct intel_uncore *uncore = &i915->uncore;
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int i;
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if (!s)
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return;
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/* GAM 0x4000-0x4770 */
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intel_uncore_write(uncore, GEN7_WR_WATERMARK, s->wr_watermark);
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intel_uncore_write(uncore, GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
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intel_uncore_write(uncore, ARB_MODE, s->arb_mode | (0xffff << 16));
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intel_uncore_write(uncore, GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
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intel_uncore_write(uncore, GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
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for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
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intel_uncore_write(uncore, GEN7_LRA_LIMITS(i), s->lra_limits[i]);
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intel_uncore_write(uncore, GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
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intel_uncore_write(uncore, GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
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intel_uncore_write(uncore, RENDER_HWS_PGA_GEN7, s->render_hwsp);
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intel_uncore_write(uncore, GAM_ECOCHK, s->ecochk);
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intel_uncore_write(uncore, BSD_HWS_PGA_GEN7, s->bsd_hwsp);
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intel_uncore_write(uncore, BLT_HWS_PGA_GEN7, s->blt_hwsp);
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intel_uncore_write(uncore, GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
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/* MBC 0x9024-0x91D0, 0x8500 */
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intel_uncore_write(uncore, VLV_G3DCTL, s->g3dctl);
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intel_uncore_write(uncore, VLV_GSCKGCTL, s->gsckgctl);
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intel_uncore_write(uncore, GEN6_MBCTL, s->mbctl);
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/* GCP 0x9400-0x9424, 0x8100-0x810C */
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intel_uncore_write(uncore, GEN6_UCGCTL1, s->ucgctl1);
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intel_uncore_write(uncore, GEN6_UCGCTL3, s->ucgctl3);
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intel_uncore_write(uncore, GEN6_RCGCTL1, s->rcgctl1);
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intel_uncore_write(uncore, GEN6_RCGCTL2, s->rcgctl2);
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intel_uncore_write(uncore, GEN6_RSTCTL, s->rstctl);
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intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl);
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/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
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intel_uncore_write(uncore, GEN6_GFXPAUSE, s->gfxpause);
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intel_uncore_write(uncore, GEN6_RPDEUHWTC, s->rpdeuhwtc);
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intel_uncore_write(uncore, GEN6_RPDEUC, s->rpdeuc);
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intel_uncore_write(uncore, ECOBUS, s->ecobus);
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intel_uncore_write(uncore, VLV_PWRDWNUPCTL, s->pwrdwnupctl);
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intel_uncore_write(uncore, GEN6_RP_DOWN_TIMEOUT, s->rp_down_timeout);
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intel_uncore_write(uncore, GEN6_RPDEUCSW, s->rp_deucsw);
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intel_uncore_write(uncore, GEN6_RCUBMABDTMR, s->rcubmabdtmr);
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intel_uncore_write(uncore, VLV_RCEDATA, s->rcedata);
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intel_uncore_write(uncore, VLV_SPAREG2H, s->spare2gh);
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/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
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intel_uncore_write(uncore, GTIMR, s->gt_imr);
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intel_uncore_write(uncore, GTIER, s->gt_ier);
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intel_uncore_write(uncore, GEN6_PMIMR, s->pm_imr);
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intel_uncore_write(uncore, GEN6_PMIER, s->pm_ier);
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for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
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intel_uncore_write(uncore, GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
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/* GT SA CZ domain, 0x100000-0x138124 */
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intel_uncore_write(uncore, TILECTL, s->tilectl);
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intel_uncore_write(uncore, GTFIFOCTL, s->gt_fifoctl);
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/*
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* Preserve the GT allow wake and GFX force clock bit, they are not
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* be restored, as they are used to control the s0ix suspend/resume
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* sequence by the caller.
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*/
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intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, ~VLV_GTLC_ALLOWWAKEREQ,
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s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ);
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intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, ~VLV_GFX_CLK_FORCE_ON_BIT,
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s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT);
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intel_uncore_write(uncore, VLV_PMWGICZ, s->pmwgicz);
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/* Gunit-Display CZ domain, 0x182028-0x1821CF */
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intel_uncore_write(uncore, VLV_GU_CTL0, s->gu_ctl0);
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intel_uncore_write(uncore, VLV_GU_CTL1, s->gu_ctl1);
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intel_uncore_write(uncore, VLV_PCBR, s->pcbr);
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intel_uncore_write(uncore, VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
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}
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static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
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u32 mask, u32 val)
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{
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i915_reg_t reg = VLV_GTLC_PW_STATUS;
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u32 reg_value;
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int ret;
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/* The HW does not like us polling for PW_STATUS frequently, so
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* use the sleeping loop rather than risk the busy spin within
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* intel_wait_for_register().
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*
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* Transitioning between RC6 states should be at most 2ms (see
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* valleyview_enable_rps) so use a 3ms timeout.
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*/
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ret = wait_for(((reg_value =
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intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
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== val, 3);
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/* just trace the final value */
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trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
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return ret;
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}
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static int vlv_force_gfx_clock(struct drm_i915_private *i915, bool force_on)
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{
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struct intel_uncore *uncore = &i915->uncore;
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int err;
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intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, VLV_GFX_CLK_FORCE_ON_BIT,
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force_on ? VLV_GFX_CLK_FORCE_ON_BIT : 0);
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if (!force_on)
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return 0;
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err = intel_wait_for_register(uncore,
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VLV_GTLC_SURVIVABILITY_REG,
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VLV_GFX_CLK_STATUS_BIT,
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VLV_GFX_CLK_STATUS_BIT,
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20);
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if (err)
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drm_err(&i915->drm,
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"timeout waiting for GFX clock force-on (%08x)\n",
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intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG));
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return err;
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}
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static int vlv_allow_gt_wake(struct drm_i915_private *i915, bool allow)
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{
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struct intel_uncore *uncore = &i915->uncore;
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u32 mask;
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u32 val;
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int err;
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intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ,
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allow ? VLV_GTLC_ALLOWWAKEREQ : 0);
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intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL);
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mask = VLV_GTLC_ALLOWWAKEACK;
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val = allow ? mask : 0;
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err = vlv_wait_for_pw_status(i915, mask, val);
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if (err)
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drm_err(&i915->drm, "timeout disabling GT waking\n");
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return err;
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}
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static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
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bool wait_for_on)
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{
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u32 mask;
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u32 val;
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mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
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val = wait_for_on ? mask : 0;
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/*
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* RC6 transitioning can be delayed up to 2 msec (see
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* valleyview_enable_rps), use 3 msec for safety.
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*
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* This can fail to turn off the rc6 if the GPU is stuck after a failed
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* reset and we are trying to force the machine to sleep.
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*/
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if (vlv_wait_for_pw_status(dev_priv, mask, val))
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drm_dbg(&dev_priv->drm,
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"timeout waiting for GT wells to go %s\n",
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str_on_off(wait_for_on));
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}
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static void vlv_check_no_gt_access(struct drm_i915_private *i915)
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{
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struct intel_uncore *uncore = &i915->uncore;
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if (!(intel_uncore_read(uncore, VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
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return;
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drm_dbg(&i915->drm, "GT register access while GT waking disabled\n");
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intel_uncore_write(uncore, VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
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}
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int vlv_suspend_complete(struct drm_i915_private *dev_priv)
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{
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u32 mask;
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int err;
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if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
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return 0;
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/*
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* Bspec defines the following GT well on flags as debug only, so
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* don't treat them as hard failures.
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*/
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vlv_wait_for_gt_wells(dev_priv, false);
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mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
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drm_WARN_ON(&dev_priv->drm,
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(intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask);
|
|
|
|
vlv_check_no_gt_access(dev_priv);
|
|
|
|
err = vlv_force_gfx_clock(dev_priv, true);
|
|
if (err)
|
|
goto err1;
|
|
|
|
err = vlv_allow_gt_wake(dev_priv, false);
|
|
if (err)
|
|
goto err2;
|
|
|
|
vlv_save_gunit_s0ix_state(dev_priv);
|
|
|
|
err = vlv_force_gfx_clock(dev_priv, false);
|
|
if (err)
|
|
goto err2;
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
/* For safety always re-enable waking and disable gfx clock forcing */
|
|
vlv_allow_gt_wake(dev_priv, true);
|
|
err1:
|
|
vlv_force_gfx_clock(dev_priv, false);
|
|
|
|
return err;
|
|
}
|
|
|
|
int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume)
|
|
{
|
|
int err;
|
|
int ret;
|
|
|
|
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
|
|
return 0;
|
|
|
|
/*
|
|
* If any of the steps fail just try to continue, that's the best we
|
|
* can do at this point. Return the first error code (which will also
|
|
* leave RPM permanently disabled).
|
|
*/
|
|
ret = vlv_force_gfx_clock(dev_priv, true);
|
|
|
|
vlv_restore_gunit_s0ix_state(dev_priv);
|
|
|
|
err = vlv_allow_gt_wake(dev_priv, true);
|
|
if (!ret)
|
|
ret = err;
|
|
|
|
err = vlv_force_gfx_clock(dev_priv, false);
|
|
if (!ret)
|
|
ret = err;
|
|
|
|
vlv_check_no_gt_access(dev_priv);
|
|
|
|
if (rpm_resume)
|
|
intel_init_clock_gating(dev_priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int vlv_suspend_init(struct drm_i915_private *i915)
|
|
{
|
|
if (!IS_VALLEYVIEW(i915))
|
|
return 0;
|
|
|
|
/* we write all the values in the struct, so no need to zero it out */
|
|
i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
|
|
GFP_KERNEL);
|
|
if (!i915->vlv_s0ix_state)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void vlv_suspend_cleanup(struct drm_i915_private *i915)
|
|
{
|
|
if (!i915->vlv_s0ix_state)
|
|
return;
|
|
|
|
kfree(i915->vlv_s0ix_state);
|
|
i915->vlv_s0ix_state = NULL;
|
|
}
|