735 lines
19 KiB
C
735 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
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#include <linux/completion.h>
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#include <linux/circ_buf.h>
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#include <linux/list.h>
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#include "a6xx_gmu.h"
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#include "a6xx_gmu.xml.h"
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#include "a6xx_gpu.h"
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#define HFI_MSG_ID(val) [val] = #val
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static const char * const a6xx_hfi_msg_id[] = {
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HFI_MSG_ID(HFI_H2F_MSG_INIT),
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HFI_MSG_ID(HFI_H2F_MSG_FW_VERSION),
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HFI_MSG_ID(HFI_H2F_MSG_BW_TABLE),
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HFI_MSG_ID(HFI_H2F_MSG_PERF_TABLE),
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HFI_MSG_ID(HFI_H2F_MSG_TEST),
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HFI_MSG_ID(HFI_H2F_MSG_START),
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HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START),
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HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE),
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HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER),
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};
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static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu,
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struct a6xx_hfi_queue *queue, u32 *data, u32 dwords)
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{
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struct a6xx_hfi_queue_header *header = queue->header;
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u32 i, hdr, index = header->read_index;
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if (header->read_index == header->write_index) {
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header->rx_request = 1;
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return 0;
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}
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hdr = queue->data[index];
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queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index;
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/*
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* If we are to assume that the GMU firmware is in fact a rational actor
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* and is programmed to not send us a larger response than we expect
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* then we can also assume that if the header size is unexpectedly large
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* that it is due to memory corruption and/or hardware failure. In this
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* case the only reasonable course of action is to BUG() to help harden
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* the failure.
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*/
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BUG_ON(HFI_HEADER_SIZE(hdr) > dwords);
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for (i = 0; i < HFI_HEADER_SIZE(hdr); i++) {
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data[i] = queue->data[index];
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index = (index + 1) % header->size;
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}
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if (!gmu->legacy)
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index = ALIGN(index, 4) % header->size;
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header->read_index = index;
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return HFI_HEADER_SIZE(hdr);
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}
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static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
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struct a6xx_hfi_queue *queue, u32 *data, u32 dwords)
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{
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struct a6xx_hfi_queue_header *header = queue->header;
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u32 i, space, index = header->write_index;
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spin_lock(&queue->lock);
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space = CIRC_SPACE(header->write_index, header->read_index,
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header->size);
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if (space < dwords) {
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header->dropped++;
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spin_unlock(&queue->lock);
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return -ENOSPC;
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}
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queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index;
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for (i = 0; i < dwords; i++) {
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queue->data[index] = data[i];
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index = (index + 1) % header->size;
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}
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/* Cookify any non used data at the end of the write buffer */
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if (!gmu->legacy) {
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for (; index % 4; index = (index + 1) % header->size)
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queue->data[index] = 0xfafafafa;
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}
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header->write_index = index;
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spin_unlock(&queue->lock);
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);
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return 0;
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}
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static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum,
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u32 *payload, u32 payload_size)
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{
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struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE];
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u32 val;
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int ret;
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/* Wait for a response */
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ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
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val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000);
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if (ret) {
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DRM_DEV_ERROR(gmu->dev,
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"Message %s id %d timed out waiting for response\n",
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a6xx_hfi_msg_id[id], seqnum);
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return -ETIMEDOUT;
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}
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/* Clear the interrupt */
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gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR,
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A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ);
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for (;;) {
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struct a6xx_hfi_msg_response resp;
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/* Get the next packet */
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ret = a6xx_hfi_queue_read(gmu, queue, (u32 *) &resp,
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sizeof(resp) >> 2);
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/* If the queue is empty our response never made it */
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if (!ret) {
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DRM_DEV_ERROR(gmu->dev,
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"The HFI response queue is unexpectedly empty\n");
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return -ENOENT;
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}
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if (HFI_HEADER_ID(resp.header) == HFI_F2H_MSG_ERROR) {
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struct a6xx_hfi_msg_error *error =
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(struct a6xx_hfi_msg_error *) &resp;
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DRM_DEV_ERROR(gmu->dev, "GMU firmware error %d\n",
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error->code);
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continue;
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}
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if (seqnum != HFI_HEADER_SEQNUM(resp.ret_header)) {
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DRM_DEV_ERROR(gmu->dev,
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"Unexpected message id %d on the response queue\n",
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HFI_HEADER_SEQNUM(resp.ret_header));
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continue;
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}
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if (resp.error) {
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DRM_DEV_ERROR(gmu->dev,
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"Message %s id %d returned error %d\n",
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a6xx_hfi_msg_id[id], seqnum, resp.error);
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return -EINVAL;
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}
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/* All is well, copy over the buffer */
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if (payload && payload_size)
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memcpy(payload, resp.payload,
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min_t(u32, payload_size, sizeof(resp.payload)));
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return 0;
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}
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}
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static int a6xx_hfi_send_msg(struct a6xx_gmu *gmu, int id,
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void *data, u32 size, u32 *payload, u32 payload_size)
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{
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struct a6xx_hfi_queue *queue = &gmu->queues[HFI_COMMAND_QUEUE];
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int ret, dwords = size >> 2;
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u32 seqnum;
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seqnum = atomic_inc_return(&queue->seqnum) % 0xfff;
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/* First dword of the message is the message header - fill it in */
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*((u32 *) data) = (seqnum << 20) | (HFI_MSG_CMD << 16) |
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(dwords << 8) | id;
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ret = a6xx_hfi_queue_write(gmu, queue, data, dwords);
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if (ret) {
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DRM_DEV_ERROR(gmu->dev, "Unable to send message %s id %d\n",
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a6xx_hfi_msg_id[id], seqnum);
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return ret;
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}
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return a6xx_hfi_wait_for_ack(gmu, id, seqnum, payload, payload_size);
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}
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static int a6xx_hfi_send_gmu_init(struct a6xx_gmu *gmu, int boot_state)
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{
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struct a6xx_hfi_msg_gmu_init_cmd msg = { 0 };
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msg.dbg_buffer_addr = (u32) gmu->debug.iova;
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msg.dbg_buffer_size = (u32) gmu->debug.size;
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msg.boot_state = boot_state;
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return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_INIT, &msg, sizeof(msg),
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NULL, 0);
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}
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static int a6xx_hfi_get_fw_version(struct a6xx_gmu *gmu, u32 *version)
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{
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struct a6xx_hfi_msg_fw_version msg = { 0 };
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/* Currently supporting version 1.10 */
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msg.supported_version = (1 << 28) | (1 << 19) | (1 << 17);
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return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_FW_VERSION, &msg, sizeof(msg),
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version, sizeof(*version));
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}
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static int a6xx_hfi_send_perf_table_v1(struct a6xx_gmu *gmu)
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{
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struct a6xx_hfi_msg_perf_table_v1 msg = { 0 };
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int i;
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msg.num_gpu_levels = gmu->nr_gpu_freqs;
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msg.num_gmu_levels = gmu->nr_gmu_freqs;
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for (i = 0; i < gmu->nr_gpu_freqs; i++) {
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msg.gx_votes[i].vote = gmu->gx_arc_votes[i];
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msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000;
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}
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for (i = 0; i < gmu->nr_gmu_freqs; i++) {
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msg.cx_votes[i].vote = gmu->cx_arc_votes[i];
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msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000;
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}
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return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_PERF_TABLE, &msg, sizeof(msg),
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NULL, 0);
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}
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static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu)
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{
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struct a6xx_hfi_msg_perf_table msg = { 0 };
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int i;
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msg.num_gpu_levels = gmu->nr_gpu_freqs;
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msg.num_gmu_levels = gmu->nr_gmu_freqs;
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for (i = 0; i < gmu->nr_gpu_freqs; i++) {
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msg.gx_votes[i].vote = gmu->gx_arc_votes[i];
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msg.gx_votes[i].acd = 0xffffffff;
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msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000;
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}
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for (i = 0; i < gmu->nr_gmu_freqs; i++) {
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msg.cx_votes[i].vote = gmu->cx_arc_votes[i];
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msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000;
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}
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return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_PERF_TABLE, &msg, sizeof(msg),
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NULL, 0);
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}
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static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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/* Send a single "off" entry since the 618 GMU doesn't do bus scaling */
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msg->bw_level_num = 1;
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msg->ddr_cmds_num = 3;
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msg->ddr_wait_bitmask = 0x01;
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msg->ddr_cmds_addrs[0] = 0x50000;
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msg->ddr_cmds_addrs[1] = 0x5003c;
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msg->ddr_cmds_addrs[2] = 0x5000c;
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msg->ddr_cmds_data[0][0] = 0x40000000;
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msg->ddr_cmds_data[0][1] = 0x40000000;
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msg->ddr_cmds_data[0][2] = 0x40000000;
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/*
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* These are the CX (CNOC) votes - these are used by the GMU but the
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* votes are known and fixed for the target
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*/
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msg->cnoc_cmds_num = 1;
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msg->cnoc_wait_bitmask = 0x01;
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msg->cnoc_cmds_addrs[0] = 0x5007c;
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msg->cnoc_cmds_data[0][0] = 0x40000000;
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msg->cnoc_cmds_data[1][0] = 0x60000001;
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}
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static void a619_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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msg->bw_level_num = 13;
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msg->ddr_cmds_num = 3;
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msg->ddr_wait_bitmask = 0x0;
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msg->ddr_cmds_addrs[0] = 0x50000;
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msg->ddr_cmds_addrs[1] = 0x50004;
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msg->ddr_cmds_addrs[2] = 0x50080;
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msg->ddr_cmds_data[0][0] = 0x40000000;
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msg->ddr_cmds_data[0][1] = 0x40000000;
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msg->ddr_cmds_data[0][2] = 0x40000000;
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msg->ddr_cmds_data[1][0] = 0x6000030c;
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msg->ddr_cmds_data[1][1] = 0x600000db;
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msg->ddr_cmds_data[1][2] = 0x60000008;
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msg->ddr_cmds_data[2][0] = 0x60000618;
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msg->ddr_cmds_data[2][1] = 0x600001b6;
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msg->ddr_cmds_data[2][2] = 0x60000008;
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msg->ddr_cmds_data[3][0] = 0x60000925;
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msg->ddr_cmds_data[3][1] = 0x60000291;
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msg->ddr_cmds_data[3][2] = 0x60000008;
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msg->ddr_cmds_data[4][0] = 0x60000dc1;
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msg->ddr_cmds_data[4][1] = 0x600003dc;
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msg->ddr_cmds_data[4][2] = 0x60000008;
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msg->ddr_cmds_data[5][0] = 0x600010ad;
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msg->ddr_cmds_data[5][1] = 0x600004ae;
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msg->ddr_cmds_data[5][2] = 0x60000008;
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msg->ddr_cmds_data[6][0] = 0x600014c3;
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msg->ddr_cmds_data[6][1] = 0x600005d4;
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msg->ddr_cmds_data[6][2] = 0x60000008;
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msg->ddr_cmds_data[7][0] = 0x6000176a;
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msg->ddr_cmds_data[7][1] = 0x60000693;
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msg->ddr_cmds_data[7][2] = 0x60000008;
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msg->ddr_cmds_data[8][0] = 0x60001f01;
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msg->ddr_cmds_data[8][1] = 0x600008b5;
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msg->ddr_cmds_data[8][2] = 0x60000008;
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msg->ddr_cmds_data[9][0] = 0x60002940;
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msg->ddr_cmds_data[9][1] = 0x60000b95;
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msg->ddr_cmds_data[9][2] = 0x60000008;
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msg->ddr_cmds_data[10][0] = 0x60002f68;
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msg->ddr_cmds_data[10][1] = 0x60000d50;
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msg->ddr_cmds_data[10][2] = 0x60000008;
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msg->ddr_cmds_data[11][0] = 0x60003700;
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msg->ddr_cmds_data[11][1] = 0x60000f71;
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msg->ddr_cmds_data[11][2] = 0x60000008;
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msg->ddr_cmds_data[12][0] = 0x60003fce;
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msg->ddr_cmds_data[12][1] = 0x600011ea;
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msg->ddr_cmds_data[12][2] = 0x60000008;
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msg->cnoc_cmds_num = 1;
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msg->cnoc_wait_bitmask = 0x0;
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msg->cnoc_cmds_addrs[0] = 0x50054;
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msg->cnoc_cmds_data[0][0] = 0x40000000;
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}
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static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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/*
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* Send a single "off" entry just to get things running
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* TODO: bus scaling
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*/
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msg->bw_level_num = 1;
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msg->ddr_cmds_num = 3;
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msg->ddr_wait_bitmask = 0x01;
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msg->ddr_cmds_addrs[0] = 0x50000;
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msg->ddr_cmds_addrs[1] = 0x5003c;
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msg->ddr_cmds_addrs[2] = 0x5000c;
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msg->ddr_cmds_data[0][0] = 0x40000000;
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msg->ddr_cmds_data[0][1] = 0x40000000;
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msg->ddr_cmds_data[0][2] = 0x40000000;
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/*
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* These are the CX (CNOC) votes - these are used by the GMU but the
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* votes are known and fixed for the target
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*/
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msg->cnoc_cmds_num = 3;
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msg->cnoc_wait_bitmask = 0x01;
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msg->cnoc_cmds_addrs[0] = 0x50034;
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msg->cnoc_cmds_addrs[1] = 0x5007c;
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msg->cnoc_cmds_addrs[2] = 0x5004c;
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msg->cnoc_cmds_data[0][0] = 0x40000000;
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msg->cnoc_cmds_data[0][1] = 0x00000000;
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msg->cnoc_cmds_data[0][2] = 0x40000000;
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msg->cnoc_cmds_data[1][0] = 0x60000001;
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msg->cnoc_cmds_data[1][1] = 0x20000001;
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msg->cnoc_cmds_data[1][2] = 0x60000001;
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}
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static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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/*
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* Send a single "off" entry just to get things running
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* TODO: bus scaling
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*/
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msg->bw_level_num = 1;
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msg->ddr_cmds_num = 3;
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msg->ddr_wait_bitmask = 0x01;
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msg->ddr_cmds_addrs[0] = 0x50000;
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msg->ddr_cmds_addrs[1] = 0x50004;
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msg->ddr_cmds_addrs[2] = 0x5007c;
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msg->ddr_cmds_data[0][0] = 0x40000000;
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msg->ddr_cmds_data[0][1] = 0x40000000;
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msg->ddr_cmds_data[0][2] = 0x40000000;
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/*
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* These are the CX (CNOC) votes - these are used by the GMU but the
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* votes are known and fixed for the target
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*/
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msg->cnoc_cmds_num = 1;
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msg->cnoc_wait_bitmask = 0x01;
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msg->cnoc_cmds_addrs[0] = 0x500a4;
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msg->cnoc_cmds_data[0][0] = 0x40000000;
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msg->cnoc_cmds_data[1][0] = 0x60000001;
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}
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static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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/*
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* Send a single "off" entry just to get things running
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* TODO: bus scaling
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*/
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msg->bw_level_num = 1;
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msg->ddr_cmds_num = 3;
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msg->ddr_wait_bitmask = 0x01;
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msg->ddr_cmds_addrs[0] = 0x50004;
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msg->ddr_cmds_addrs[1] = 0x500a0;
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msg->ddr_cmds_addrs[2] = 0x50000;
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|
msg->ddr_cmds_data[0][0] = 0x40000000;
|
|
msg->ddr_cmds_data[0][1] = 0x40000000;
|
|
msg->ddr_cmds_data[0][2] = 0x40000000;
|
|
|
|
/*
|
|
* These are the CX (CNOC) votes - these are used by the GMU but the
|
|
* votes are known and fixed for the target
|
|
*/
|
|
msg->cnoc_cmds_num = 1;
|
|
msg->cnoc_wait_bitmask = 0x01;
|
|
|
|
msg->cnoc_cmds_addrs[0] = 0x50070;
|
|
msg->cnoc_cmds_data[0][0] = 0x40000000;
|
|
msg->cnoc_cmds_data[1][0] = 0x60000001;
|
|
}
|
|
|
|
static void adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
|
|
{
|
|
/*
|
|
* Send a single "off" entry just to get things running
|
|
* TODO: bus scaling
|
|
*/
|
|
msg->bw_level_num = 1;
|
|
|
|
msg->ddr_cmds_num = 3;
|
|
msg->ddr_wait_bitmask = 0x07;
|
|
|
|
msg->ddr_cmds_addrs[0] = 0x50004;
|
|
msg->ddr_cmds_addrs[1] = 0x50000;
|
|
msg->ddr_cmds_addrs[2] = 0x50088;
|
|
|
|
msg->ddr_cmds_data[0][0] = 0x40000000;
|
|
msg->ddr_cmds_data[0][1] = 0x40000000;
|
|
msg->ddr_cmds_data[0][2] = 0x40000000;
|
|
|
|
/*
|
|
* These are the CX (CNOC) votes - these are used by the GMU but the
|
|
* votes are known and fixed for the target
|
|
*/
|
|
msg->cnoc_cmds_num = 1;
|
|
msg->cnoc_wait_bitmask = 0x01;
|
|
|
|
msg->cnoc_cmds_addrs[0] = 0x5006c;
|
|
msg->cnoc_cmds_data[0][0] = 0x40000000;
|
|
msg->cnoc_cmds_data[1][0] = 0x60000001;
|
|
}
|
|
static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
|
|
{
|
|
/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
|
|
msg->bw_level_num = 1;
|
|
|
|
msg->ddr_cmds_num = 3;
|
|
msg->ddr_wait_bitmask = 0x07;
|
|
|
|
msg->ddr_cmds_addrs[0] = 0x50000;
|
|
msg->ddr_cmds_addrs[1] = 0x5005c;
|
|
msg->ddr_cmds_addrs[2] = 0x5000c;
|
|
|
|
msg->ddr_cmds_data[0][0] = 0x40000000;
|
|
msg->ddr_cmds_data[0][1] = 0x40000000;
|
|
msg->ddr_cmds_data[0][2] = 0x40000000;
|
|
|
|
/*
|
|
* These are the CX (CNOC) votes. This is used but the values for the
|
|
* sdm845 GMU are known and fixed so we can hard code them.
|
|
*/
|
|
|
|
msg->cnoc_cmds_num = 3;
|
|
msg->cnoc_wait_bitmask = 0x05;
|
|
|
|
msg->cnoc_cmds_addrs[0] = 0x50034;
|
|
msg->cnoc_cmds_addrs[1] = 0x5007c;
|
|
msg->cnoc_cmds_addrs[2] = 0x5004c;
|
|
|
|
msg->cnoc_cmds_data[0][0] = 0x40000000;
|
|
msg->cnoc_cmds_data[0][1] = 0x00000000;
|
|
msg->cnoc_cmds_data[0][2] = 0x40000000;
|
|
|
|
msg->cnoc_cmds_data[1][0] = 0x60000001;
|
|
msg->cnoc_cmds_data[1][1] = 0x20000001;
|
|
msg->cnoc_cmds_data[1][2] = 0x60000001;
|
|
}
|
|
|
|
|
|
static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
|
|
{
|
|
struct a6xx_hfi_msg_bw_table msg = { 0 };
|
|
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
|
|
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
|
|
|
|
if (adreno_is_a618(adreno_gpu))
|
|
a618_build_bw_table(&msg);
|
|
else if (adreno_is_a619(adreno_gpu))
|
|
a619_build_bw_table(&msg);
|
|
else if (adreno_is_a640_family(adreno_gpu))
|
|
a640_build_bw_table(&msg);
|
|
else if (adreno_is_a650(adreno_gpu))
|
|
a650_build_bw_table(&msg);
|
|
else if (adreno_is_7c3(adreno_gpu))
|
|
adreno_7c3_build_bw_table(&msg);
|
|
else if (adreno_is_a660(adreno_gpu))
|
|
a660_build_bw_table(&msg);
|
|
else
|
|
a6xx_build_bw_table(&msg);
|
|
|
|
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_BW_TABLE, &msg, sizeof(msg),
|
|
NULL, 0);
|
|
}
|
|
|
|
static int a6xx_hfi_send_test(struct a6xx_gmu *gmu)
|
|
{
|
|
struct a6xx_hfi_msg_test msg = { 0 };
|
|
|
|
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TEST, &msg, sizeof(msg),
|
|
NULL, 0);
|
|
}
|
|
|
|
static int a6xx_hfi_send_start(struct a6xx_gmu *gmu)
|
|
{
|
|
struct a6xx_hfi_msg_start msg = { 0 };
|
|
|
|
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_START, &msg, sizeof(msg),
|
|
NULL, 0);
|
|
}
|
|
|
|
static int a6xx_hfi_send_core_fw_start(struct a6xx_gmu *gmu)
|
|
{
|
|
struct a6xx_hfi_msg_core_fw_start msg = { 0 };
|
|
|
|
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CORE_FW_START, &msg,
|
|
sizeof(msg), NULL, 0);
|
|
}
|
|
|
|
int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index)
|
|
{
|
|
struct a6xx_hfi_gx_bw_perf_vote_cmd msg = { 0 };
|
|
|
|
msg.ack_type = 1; /* blocking */
|
|
msg.freq = index;
|
|
msg.bw = 0; /* TODO: bus scaling */
|
|
|
|
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_GX_BW_PERF_VOTE, &msg,
|
|
sizeof(msg), NULL, 0);
|
|
}
|
|
|
|
int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu)
|
|
{
|
|
struct a6xx_hfi_prep_slumber_cmd msg = { 0 };
|
|
|
|
/* TODO: should freq and bw fields be non-zero ? */
|
|
|
|
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_PREPARE_SLUMBER, &msg,
|
|
sizeof(msg), NULL, 0);
|
|
}
|
|
|
|
static int a6xx_hfi_start_v1(struct a6xx_gmu *gmu, int boot_state)
|
|
{
|
|
int ret;
|
|
|
|
ret = a6xx_hfi_send_gmu_init(gmu, boot_state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = a6xx_hfi_get_fw_version(gmu, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* We have to get exchange version numbers per the sequence but at this
|
|
* point th kernel driver doesn't need to know the exact version of
|
|
* the GMU firmware
|
|
*/
|
|
|
|
ret = a6xx_hfi_send_perf_table_v1(gmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = a6xx_hfi_send_bw_table(gmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Let the GMU know that there won't be any more HFI messages until next
|
|
* boot
|
|
*/
|
|
a6xx_hfi_send_test(gmu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state)
|
|
{
|
|
int ret;
|
|
|
|
if (gmu->legacy)
|
|
return a6xx_hfi_start_v1(gmu, boot_state);
|
|
|
|
|
|
ret = a6xx_hfi_send_perf_table(gmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = a6xx_hfi_send_bw_table(gmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = a6xx_hfi_send_core_fw_start(gmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Downstream driver sends this in its "a6xx_hw_init" equivalent,
|
|
* but seems to be no harm in sending it here
|
|
*/
|
|
ret = a6xx_hfi_send_start(gmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void a6xx_hfi_stop(struct a6xx_gmu *gmu)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) {
|
|
struct a6xx_hfi_queue *queue = &gmu->queues[i];
|
|
|
|
if (!queue->header)
|
|
continue;
|
|
|
|
if (queue->header->read_index != queue->header->write_index)
|
|
DRM_DEV_ERROR(gmu->dev, "HFI queue %d is not empty\n", i);
|
|
|
|
queue->header->read_index = 0;
|
|
queue->header->write_index = 0;
|
|
|
|
memset(&queue->history, 0xff, sizeof(queue->history));
|
|
queue->history_idx = 0;
|
|
}
|
|
}
|
|
|
|
static void a6xx_hfi_queue_init(struct a6xx_hfi_queue *queue,
|
|
struct a6xx_hfi_queue_header *header, void *virt, u64 iova,
|
|
u32 id)
|
|
{
|
|
spin_lock_init(&queue->lock);
|
|
queue->header = header;
|
|
queue->data = virt;
|
|
atomic_set(&queue->seqnum, 0);
|
|
|
|
memset(&queue->history, 0xff, sizeof(queue->history));
|
|
queue->history_idx = 0;
|
|
|
|
/* Set up the shared memory header */
|
|
header->iova = iova;
|
|
header->type = 10 << 8 | id;
|
|
header->status = 1;
|
|
header->size = SZ_4K >> 2;
|
|
header->msg_size = 0;
|
|
header->dropped = 0;
|
|
header->rx_watermark = 1;
|
|
header->tx_watermark = 1;
|
|
header->rx_request = 1;
|
|
header->tx_request = 0;
|
|
header->read_index = 0;
|
|
header->write_index = 0;
|
|
}
|
|
|
|
void a6xx_hfi_init(struct a6xx_gmu *gmu)
|
|
{
|
|
struct a6xx_gmu_bo *hfi = &gmu->hfi;
|
|
struct a6xx_hfi_queue_table_header *table = hfi->virt;
|
|
struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table);
|
|
u64 offset;
|
|
int table_size;
|
|
|
|
/*
|
|
* The table size is the size of the table header plus all of the queue
|
|
* headers
|
|
*/
|
|
table_size = sizeof(*table);
|
|
table_size += (ARRAY_SIZE(gmu->queues) *
|
|
sizeof(struct a6xx_hfi_queue_header));
|
|
|
|
table->version = 0;
|
|
table->size = table_size;
|
|
/* First queue header is located immediately after the table header */
|
|
table->qhdr0_offset = sizeof(*table) >> 2;
|
|
table->qhdr_size = sizeof(struct a6xx_hfi_queue_header) >> 2;
|
|
table->num_queues = ARRAY_SIZE(gmu->queues);
|
|
table->active_queues = ARRAY_SIZE(gmu->queues);
|
|
|
|
/* Command queue */
|
|
offset = SZ_4K;
|
|
a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset,
|
|
hfi->iova + offset, 0);
|
|
|
|
/* GMU response queue */
|
|
offset += SZ_4K;
|
|
a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset,
|
|
hfi->iova + offset, gmu->legacy ? 4 : 1);
|
|
}
|