467 lines
9.7 KiB
C
467 lines
9.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_MDSS_H
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#define _DPU_HW_MDSS_H
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include "msm_drv.h"
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#define DPU_DBG_NAME "dpu"
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#define DPU_NONE 0
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#ifndef DPU_CSC_MATRIX_COEFF_SIZE
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#define DPU_CSC_MATRIX_COEFF_SIZE 9
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#endif
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#ifndef DPU_CSC_CLAMP_SIZE
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#define DPU_CSC_CLAMP_SIZE 6
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#endif
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#ifndef DPU_CSC_BIAS_SIZE
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#define DPU_CSC_BIAS_SIZE 3
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#endif
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#ifndef DPU_MAX_PLANES
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#define DPU_MAX_PLANES 4
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#endif
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#define PIPES_PER_STAGE 2
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#ifndef DPU_MAX_DE_CURVES
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#define DPU_MAX_DE_CURVES 3
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#endif
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enum dpu_format_flags {
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DPU_FORMAT_FLAG_YUV_BIT,
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DPU_FORMAT_FLAG_DX_BIT,
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DPU_FORMAT_FLAG_COMPRESSED_BIT,
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DPU_FORMAT_FLAG_BIT_MAX,
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};
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#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
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#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
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#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
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#define DPU_FORMAT_IS_YUV(X) \
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(test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
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#define DPU_FORMAT_IS_DX(X) \
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(test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
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#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
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#define DPU_FORMAT_IS_TILE(X) \
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(((X)->fetch_mode == DPU_FETCH_UBWC) && \
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!test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
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#define DPU_FORMAT_IS_UBWC(X) \
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(((X)->fetch_mode == DPU_FETCH_UBWC) && \
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test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
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#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
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#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
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#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
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#define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
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#define DPU_BLEND_FG_INV_ALPHA (1 << 2)
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#define DPU_BLEND_FG_MOD_ALPHA (1 << 3)
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#define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4)
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#define DPU_BLEND_FG_TRANSP_EN (1 << 5)
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#define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8)
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#define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8)
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#define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)
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#define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)
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#define DPU_BLEND_BG_INV_ALPHA (1 << 10)
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#define DPU_BLEND_BG_MOD_ALPHA (1 << 11)
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#define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12)
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#define DPU_BLEND_BG_TRANSP_EN (1 << 13)
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#define DPU_VSYNC0_SOURCE_GPIO 0
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#define DPU_VSYNC1_SOURCE_GPIO 1
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#define DPU_VSYNC2_SOURCE_GPIO 2
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#define DPU_VSYNC_SOURCE_INTF_0 3
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#define DPU_VSYNC_SOURCE_INTF_1 4
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#define DPU_VSYNC_SOURCE_INTF_2 5
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#define DPU_VSYNC_SOURCE_INTF_3 6
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#define DPU_VSYNC_SOURCE_WD_TIMER_4 11
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#define DPU_VSYNC_SOURCE_WD_TIMER_3 12
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#define DPU_VSYNC_SOURCE_WD_TIMER_2 13
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#define DPU_VSYNC_SOURCE_WD_TIMER_1 14
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#define DPU_VSYNC_SOURCE_WD_TIMER_0 15
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enum dpu_hw_blk_type {
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DPU_HW_BLK_TOP = 0,
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DPU_HW_BLK_SSPP,
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DPU_HW_BLK_LM,
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DPU_HW_BLK_CTL,
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DPU_HW_BLK_PINGPONG,
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DPU_HW_BLK_INTF,
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DPU_HW_BLK_WB,
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DPU_HW_BLK_DSPP,
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DPU_HW_BLK_MERGE_3D,
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DPU_HW_BLK_DSC,
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DPU_HW_BLK_MAX,
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};
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enum dpu_mdp {
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MDP_TOP = 0x1,
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MDP_MAX,
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};
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enum dpu_sspp {
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SSPP_NONE,
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SSPP_VIG0,
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SSPP_VIG1,
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SSPP_VIG2,
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SSPP_VIG3,
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SSPP_RGB0,
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SSPP_RGB1,
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SSPP_RGB2,
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SSPP_RGB3,
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SSPP_DMA0,
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SSPP_DMA1,
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SSPP_DMA2,
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SSPP_DMA3,
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SSPP_DMA4,
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SSPP_DMA5,
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SSPP_CURSOR0,
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SSPP_CURSOR1,
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SSPP_MAX
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};
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enum dpu_sspp_type {
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SSPP_TYPE_VIG,
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SSPP_TYPE_RGB,
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SSPP_TYPE_DMA,
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SSPP_TYPE_CURSOR,
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SSPP_TYPE_MAX
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};
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enum dpu_lm {
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LM_0 = 1,
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LM_1,
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LM_2,
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LM_3,
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LM_4,
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LM_5,
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LM_6,
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LM_MAX
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};
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enum dpu_stage {
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DPU_STAGE_BASE = 0,
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DPU_STAGE_0,
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DPU_STAGE_1,
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DPU_STAGE_2,
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DPU_STAGE_3,
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DPU_STAGE_4,
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DPU_STAGE_5,
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DPU_STAGE_6,
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DPU_STAGE_7,
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DPU_STAGE_8,
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DPU_STAGE_9,
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DPU_STAGE_10,
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DPU_STAGE_MAX
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};
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enum dpu_dspp {
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DSPP_0 = 1,
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DSPP_1,
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DSPP_2,
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DSPP_3,
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DSPP_MAX
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};
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enum dpu_ctl {
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CTL_0 = 1,
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CTL_1,
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CTL_2,
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CTL_3,
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CTL_4,
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CTL_5,
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CTL_MAX
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};
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enum dpu_dsc {
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DSC_NONE = 0,
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DSC_0,
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DSC_1,
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DSC_2,
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DSC_3,
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DSC_4,
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DSC_5,
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DSC_MAX
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};
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enum dpu_pingpong {
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PINGPONG_0 = 1,
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PINGPONG_1,
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PINGPONG_2,
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PINGPONG_3,
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PINGPONG_4,
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PINGPONG_5,
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PINGPONG_6,
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PINGPONG_7,
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PINGPONG_S0,
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PINGPONG_MAX
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};
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enum dpu_merge_3d {
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MERGE_3D_0 = 1,
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MERGE_3D_1,
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MERGE_3D_2,
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MERGE_3D_3,
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MERGE_3D_MAX
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};
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enum dpu_intf {
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INTF_0 = 1,
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INTF_1,
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INTF_2,
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INTF_3,
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INTF_4,
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INTF_5,
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INTF_6,
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INTF_7,
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INTF_8,
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INTF_MAX
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};
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/*
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* Historically these values correspond to the values written to the
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* DISP_INTF_SEL register, which had to programmed manually. On newer MDP
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* generations this register is NOP, but we keep the values for historical
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* reasons.
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*/
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enum dpu_intf_type {
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INTF_NONE = 0x0,
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INTF_DSI = 0x1,
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INTF_HDMI = 0x3,
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INTF_LCDC = 0x5,
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/* old eDP found on 8x74 and 8x84 */
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INTF_EDP = 0x9,
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/* both DP and eDP, handled by the new DP driver */
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INTF_DP = 0xa,
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/* virtual interfaces */
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INTF_WB = 0x100,
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};
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enum dpu_intf_mode {
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INTF_MODE_NONE = 0,
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INTF_MODE_CMD,
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INTF_MODE_VIDEO,
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INTF_MODE_WB_BLOCK,
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INTF_MODE_WB_LINE,
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INTF_MODE_MAX
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};
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enum dpu_wb {
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WB_0 = 1,
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WB_1,
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WB_2,
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WB_3,
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WB_MAX
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};
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enum dpu_cwb {
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CWB_0 = 0x1,
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CWB_1,
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CWB_2,
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CWB_3,
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CWB_MAX
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};
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enum dpu_wd_timer {
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WD_TIMER_0 = 0x1,
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WD_TIMER_1,
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WD_TIMER_2,
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WD_TIMER_3,
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WD_TIMER_4,
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WD_TIMER_5,
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WD_TIMER_MAX
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};
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enum dpu_vbif {
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VBIF_RT,
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VBIF_NRT,
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VBIF_MAX,
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};
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/**
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* DPU HW,Component order color map
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*/
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enum {
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C0_G_Y = 0,
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C1_B_Cb = 1,
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C2_R_Cr = 2,
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C3_ALPHA = 3
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};
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/**
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* enum dpu_plane_type - defines how the color component pixel packing
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* @DPU_PLANE_INTERLEAVED : Color components in single plane
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* @DPU_PLANE_PLANAR : Color component in separate planes
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* @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
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*/
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enum dpu_plane_type {
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DPU_PLANE_INTERLEAVED,
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DPU_PLANE_PLANAR,
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DPU_PLANE_PSEUDO_PLANAR,
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};
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/**
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* enum dpu_chroma_samp_type - chroma sub-samplng type
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* @DPU_CHROMA_RGB : No chroma subsampling
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* @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
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* @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
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* @DPU_CHROMA_420 : 420 subsampling
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*/
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enum dpu_chroma_samp_type {
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DPU_CHROMA_RGB,
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DPU_CHROMA_H2V1,
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DPU_CHROMA_H1V2,
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DPU_CHROMA_420
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};
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/**
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* dpu_fetch_type - Defines How DPU HW fetches data
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* @DPU_FETCH_LINEAR : fetch is line by line
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* @DPU_FETCH_TILE : fetches data in Z order from a tile
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* @DPU_FETCH_UBWC : fetch and decompress data
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*/
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enum dpu_fetch_type {
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DPU_FETCH_LINEAR,
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DPU_FETCH_TILE,
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DPU_FETCH_UBWC
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};
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/**
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* Value of enum chosen to fit the number of bits
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* expected by the HW programming.
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*/
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enum {
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COLOR_ALPHA_1BIT = 0,
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COLOR_ALPHA_4BIT = 1,
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COLOR_4BIT = 0,
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COLOR_5BIT = 1, /* No 5-bit Alpha */
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COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
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COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
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};
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/**
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* enum dpu_3d_blend_mode
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* Desribes how the 3d data is blended
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* @BLEND_3D_NONE : 3d blending not enabled
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* @BLEND_3D_FRAME_INT : Frame interleaving
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* @BLEND_3D_H_ROW_INT : Horizontal row interleaving
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* @BLEND_3D_V_ROW_INT : vertical row interleaving
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* @BLEND_3D_COL_INT : column interleaving
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* @BLEND_3D_MAX :
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*/
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enum dpu_3d_blend_mode {
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BLEND_3D_NONE = 0,
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BLEND_3D_FRAME_INT,
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BLEND_3D_H_ROW_INT,
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BLEND_3D_V_ROW_INT,
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BLEND_3D_COL_INT,
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BLEND_3D_MAX
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};
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/** struct dpu_format - defines the format configuration which
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* allows DPU HW to correctly fetch and decode the format
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* @base: base msm_format structure containing fourcc code
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* @fetch_planes: how the color components are packed in pixel format
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* @element: element color ordering
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* @bits: element bit widths
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* @chroma_sample: chroma sub-samplng type
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* @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
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* @unpack_tight: 0 for loose, 1 for tight
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* @unpack_count: 0 = 1 component, 1 = 2 component
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* @bpp: bytes per pixel
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* @alpha_enable: whether the format has an alpha channel
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* @num_planes: number of planes (including meta data planes)
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* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
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* @flag: usage bit flags
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* @tile_width: format tile width
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* @tile_height: format tile height
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*/
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struct dpu_format {
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struct msm_format base;
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enum dpu_plane_type fetch_planes;
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u8 element[DPU_MAX_PLANES];
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u8 bits[DPU_MAX_PLANES];
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enum dpu_chroma_samp_type chroma_sample;
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u8 unpack_align_msb;
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u8 unpack_tight;
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u8 unpack_count;
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u8 bpp;
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u8 alpha_enable;
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u8 num_planes;
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enum dpu_fetch_type fetch_mode;
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DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
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u16 tile_width;
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u16 tile_height;
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};
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#define to_dpu_format(x) container_of(x, struct dpu_format, base)
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/**
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* struct dpu_hw_fmt_layout - format information of the source pixel data
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* @format: pixel format parameters
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* @num_planes: number of planes (including meta data planes)
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* @width: image width
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* @height: image height
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* @total_size: total size in bytes
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* @plane_addr: address of each plane
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* @plane_size: length of each plane
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* @plane_pitch: pitch of each plane
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*/
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struct dpu_hw_fmt_layout {
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const struct dpu_format *format;
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uint32_t num_planes;
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uint32_t width;
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uint32_t height;
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uint32_t total_size;
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uint32_t plane_addr[DPU_MAX_PLANES];
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uint32_t plane_size[DPU_MAX_PLANES];
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uint32_t plane_pitch[DPU_MAX_PLANES];
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};
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struct dpu_csc_cfg {
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/* matrix coefficients in S15.16 format */
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uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE];
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uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE];
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uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE];
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uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE];
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uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE];
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};
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/**
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* struct dpu_mdss_color - mdss color description
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* color 0 : green
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* color 1 : blue
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* color 2 : red
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* color 3 : alpha
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*/
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struct dpu_mdss_color {
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u32 color_0;
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u32 color_1;
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u32 color_2;
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u32 color_3;
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};
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/*
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* Define bit masks for h/w logging.
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*/
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#define DPU_DBG_MASK_NONE (1 << 0)
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#define DPU_DBG_MASK_INTF (1 << 1)
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#define DPU_DBG_MASK_LM (1 << 2)
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#define DPU_DBG_MASK_CTL (1 << 3)
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#define DPU_DBG_MASK_PINGPONG (1 << 4)
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#define DPU_DBG_MASK_SSPP (1 << 5)
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#define DPU_DBG_MASK_WB (1 << 6)
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#define DPU_DBG_MASK_TOP (1 << 7)
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#define DPU_DBG_MASK_VBIF (1 << 8)
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#define DPU_DBG_MASK_ROT (1 << 9)
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#define DPU_DBG_MASK_DSPP (1 << 10)
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#define DPU_DBG_MASK_DSC (1 << 11)
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#endif /* _DPU_HW_MDSS_H */
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