106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
#ifndef __NVFW_SEC2_H__
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#define __NVFW_SEC2_H__
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struct nv_sec2_args {
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u32 freq_hz;
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u32 falc_trace_size;
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u32 falc_trace_dma_base;
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u32 falc_trace_dma_idx;
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bool secure_mode;
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};
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#define NV_SEC2_UNIT_INIT 0x01
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#define NV_SEC2_UNIT_UNLOAD 0x06
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#define NV_SEC2_UNIT_ACR 0x08
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struct nv_sec2_init_msg {
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struct nvfw_falcon_msg hdr;
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#define NV_SEC2_INIT_MSG_INIT 0x00
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u8 msg_type;
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u8 num_queues;
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u16 os_debug_entry_point;
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struct {
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u32 offset;
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u16 size;
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u8 index;
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#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
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#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
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u8 id;
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} queue_info[2];
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u32 sw_managed_area_offset;
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u16 sw_managed_area_size;
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};
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struct nv_sec2_init_msg_v1 {
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struct nvfw_falcon_msg hdr;
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#define NV_SEC2_INIT_MSG_INIT 0x00
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u8 msg_type;
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u8 num_queues;
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u16 os_debug_entry_point;
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struct {
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u32 offset;
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u16 size;
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u8 index;
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#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
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#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
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u8 id;
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} queue_info[2];
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u32 sw_managed_area_offset;
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u16 sw_managed_area_size;
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u32 unkn[8];
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};
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struct nv_sec2_acr_cmd {
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struct nvfw_falcon_cmd hdr;
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#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00
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u8 cmd_type;
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};
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struct nv_sec2_acr_msg {
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struct nvfw_falcon_cmd hdr;
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u8 msg_type;
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};
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struct nv_sec2_acr_bootstrap_falcon_cmd {
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struct nv_sec2_acr_cmd cmd;
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#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
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#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
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u32 flags;
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u32 falcon_id;
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};
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struct nv_sec2_acr_bootstrap_falcon_msg {
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struct nv_sec2_acr_msg msg;
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u32 error_code;
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u32 falcon_id;
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};
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#define NV_SEC2_UNIT_V2_INIT 0x01
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#define NV_SEC2_UNIT_V2_UNLOAD 0x05
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#define NV_SEC2_UNIT_V2_ACR 0x07
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struct nv_sec2_acr_bootstrap_falcon_cmd_v1 {
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struct nv_sec2_acr_cmd cmd;
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#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
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#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
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u32 flags;
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u32 falcon_id;
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u32 unkn08;
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u32 unkn0c;
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};
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struct nv_sec2_acr_bootstrap_falcon_msg_v1 {
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struct nv_sec2_acr_msg msg;
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u32 error_code;
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u32 falcon_id;
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u32 unkn08;
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};
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#endif
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