808 lines
22 KiB
C
808 lines
22 KiB
C
/*
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* Copyright 2014 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "dp.h"
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#include "conn.h"
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#include "head.h"
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#include "ior.h"
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#include <subdev/bios.h>
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#include <subdev/bios/init.h>
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#include <subdev/gpio.h>
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#include <subdev/i2c.h>
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#include <nvif/event.h>
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/* IED scripts are no longer used by UEFI/RM from Ampere, but have been updated for
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* the x86 option ROM. However, the relevant VBIOS table versions weren't modified,
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* so we're unable to detect this in a nice way.
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*/
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#define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
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struct lt_state {
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struct nvkm_outp *outp;
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int repeaters;
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int repeater;
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u8 stat[6];
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u8 conf[4];
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bool pc2;
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u8 pc2stat;
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u8 pc2conf[2];
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};
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static int
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nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)
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{
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struct nvkm_outp *outp = lt->outp;
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u32 addr;
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int ret;
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usleep_range(delay, delay * 2);
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if (lt->repeater)
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addr = DPCD_LTTPR_LANE0_1_STATUS(lt->repeater);
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else
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addr = DPCD_LS02;
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ret = nvkm_rdaux(outp->dp.aux, addr, <->stat[0], 3);
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if (ret)
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return ret;
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if (lt->repeater)
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addr = DPCD_LTTPR_LANE0_1_ADJUST(lt->repeater);
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else
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addr = DPCD_LS06;
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ret = nvkm_rdaux(outp->dp.aux, addr, <->stat[4], 2);
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if (ret)
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return ret;
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if (pc) {
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ret = nvkm_rdaux(outp->dp.aux, DPCD_LS0C, <->pc2stat, 1);
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if (ret)
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lt->pc2stat = 0x00;
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OUTP_TRACE(outp, "status %6ph pc2 %02x", lt->stat, lt->pc2stat);
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} else {
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OUTP_TRACE(outp, "status %6ph", lt->stat);
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}
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return 0;
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}
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static int
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nvkm_dp_train_drive(struct lt_state *lt, bool pc)
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{
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struct nvkm_outp *outp = lt->outp;
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struct nvkm_ior *ior = outp->ior;
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struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios;
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struct nvbios_dpout info;
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struct nvbios_dpcfg ocfg;
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u8 ver, hdr, cnt, len;
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u32 addr;
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u32 data;
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int ret, i;
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for (i = 0; i < ior->dp.nr; i++) {
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u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
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u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3;
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u8 lpre = (lane & 0x0c) >> 2;
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u8 lvsw = (lane & 0x03) >> 0;
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u8 hivs = 3 - lpre;
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u8 hipe = 3;
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u8 hipc = 3;
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if (lpc2 >= hipc)
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lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
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if (lpre >= hipe) {
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lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
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lvsw = hivs = 3 - (lpre & 3);
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} else
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if (lvsw >= hivs) {
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lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
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}
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lt->conf[i] = (lpre << 3) | lvsw;
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lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
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OUTP_TRACE(outp, "config lane %d %02x %02x", i, lt->conf[i], lpc2);
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if (lt->repeater != lt->repeaters)
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continue;
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data = nvbios_dpout_match(bios, outp->info.hasht, outp->info.hashm,
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&ver, &hdr, &cnt, &len, &info);
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if (!data)
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continue;
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data = nvbios_dpcfg_match(bios, data, lpc2 & 3, lvsw & 3, lpre & 3,
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&ver, &hdr, &cnt, &len, &ocfg);
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if (!data)
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continue;
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ior->func->dp->drive(ior, i, ocfg.pc, ocfg.dc, ocfg.pe, ocfg.tx_pu);
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}
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if (lt->repeater)
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addr = DPCD_LTTPR_LANE0_SET(lt->repeater);
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else
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addr = DPCD_LC03(0);
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ret = nvkm_wraux(outp->dp.aux, addr, lt->conf, 4);
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if (ret)
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return ret;
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if (pc) {
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ret = nvkm_wraux(outp->dp.aux, DPCD_LC0F, lt->pc2conf, 2);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void
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nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
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{
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struct nvkm_outp *outp = lt->outp;
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u32 addr;
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u8 sink_tp;
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OUTP_TRACE(outp, "training pattern %d", pattern);
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outp->ior->func->dp->pattern(outp->ior, pattern);
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if (lt->repeater)
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addr = DPCD_LTTPR_PATTERN_SET(lt->repeater);
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else
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addr = DPCD_LC02;
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nvkm_rdaux(outp->dp.aux, addr, &sink_tp, 1);
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sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
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sink_tp |= (pattern != 4) ? pattern : 7;
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if (pattern != 0)
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sink_tp |= DPCD_LC02_SCRAMBLING_DISABLE;
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else
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sink_tp &= ~DPCD_LC02_SCRAMBLING_DISABLE;
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nvkm_wraux(outp->dp.aux, addr, &sink_tp, 1);
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}
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static int
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nvkm_dp_train_eq(struct lt_state *lt)
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{
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struct nvkm_i2c_aux *aux = lt->outp->dp.aux;
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bool eq_done = false, cr_done = true;
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int tries = 0, usec = 0, i;
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u8 data;
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if (lt->repeater) {
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if (!nvkm_rdaux(aux, DPCD_LTTPR_AUX_RD_INTERVAL(lt->repeater), &data, sizeof(data)))
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usec = (data & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
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nvkm_dp_train_pattern(lt, 4);
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} else {
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if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 &&
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lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED)
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nvkm_dp_train_pattern(lt, 4);
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else
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if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 &&
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lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
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nvkm_dp_train_pattern(lt, 3);
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else
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nvkm_dp_train_pattern(lt, 2);
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usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
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}
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do {
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if ((tries &&
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nvkm_dp_train_drive(lt, lt->pc2)) ||
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nvkm_dp_train_sense(lt, lt->pc2, usec ? usec : 400))
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break;
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eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
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for (i = 0; i < lt->outp->ior->dp.nr && eq_done; i++) {
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u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DPCD_LS02_LANE0_CR_DONE))
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cr_done = false;
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if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
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!(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
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eq_done = false;
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}
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} while (!eq_done && cr_done && ++tries <= 5);
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return eq_done ? 0 : -1;
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}
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static int
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nvkm_dp_train_cr(struct lt_state *lt)
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{
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bool cr_done = false, abort = false;
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int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
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int tries = 0, usec = 0, i;
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nvkm_dp_train_pattern(lt, 1);
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if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater)
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usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
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do {
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if (nvkm_dp_train_drive(lt, false) ||
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nvkm_dp_train_sense(lt, false, usec ? usec : 100))
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break;
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cr_done = true;
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for (i = 0; i < lt->outp->ior->dp.nr; i++) {
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u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
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cr_done = false;
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if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
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abort = true;
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break;
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}
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}
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if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
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voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
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tries = 0;
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}
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} while (!cr_done && !abort && ++tries < 5);
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return cr_done ? 0 : -1;
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}
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static int
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nvkm_dp_train_link(struct nvkm_outp *outp, int rate)
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{
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struct nvkm_ior *ior = outp->ior;
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struct lt_state lt = {
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.outp = outp,
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.pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED,
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};
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u8 sink[2], data;
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int ret;
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OUTP_DBG(outp, "training %dx%02x", ior->dp.nr, ior->dp.bw);
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/* Select LTTPR non-transparent mode if we have a valid configuration,
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* use transparent mode otherwise.
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*/
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if (outp->dp.lttpr[0] >= 0x14) {
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data = DPCD_LTTPR_MODE_TRANSPARENT;
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nvkm_wraux(outp->dp.aux, DPCD_LTTPR_MODE, &data, sizeof(data));
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if (outp->dp.lttprs) {
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data = DPCD_LTTPR_MODE_NON_TRANSPARENT;
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nvkm_wraux(outp->dp.aux, DPCD_LTTPR_MODE, &data, sizeof(data));
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lt.repeaters = outp->dp.lttprs;
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}
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}
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/* Set desired link configuration on the sink. */
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sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0;
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sink[1] = ior->dp.nr;
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if (ior->dp.ef)
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sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
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ret = nvkm_wraux(outp->dp.aux, DPCD_LC00_LINK_BW_SET, sink, 2);
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if (ret)
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return ret;
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if (outp->dp.rate[rate].dpcd >= 0) {
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ret = nvkm_rdaux(outp->dp.aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
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if (ret)
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return ret;
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sink[0] &= ~DPCD_LC15_LINK_RATE_SET_MASK;
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sink[0] |= outp->dp.rate[rate].dpcd;
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ret = nvkm_wraux(outp->dp.aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
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if (ret)
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return ret;
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}
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/* Attempt to train the link in this configuration. */
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for (lt.repeater = lt.repeaters; lt.repeater >= 0; lt.repeater--) {
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if (lt.repeater)
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OUTP_DBG(outp, "training LTTPR%d", lt.repeater);
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else
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OUTP_DBG(outp, "training sink");
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memset(lt.stat, 0x00, sizeof(lt.stat));
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ret = nvkm_dp_train_cr(<);
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if (ret == 0)
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ret = nvkm_dp_train_eq(<);
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nvkm_dp_train_pattern(<, 0);
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}
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return ret;
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}
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static int
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nvkm_dp_train_links(struct nvkm_outp *outp, int rate)
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{
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struct nvkm_ior *ior = outp->ior;
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struct nvkm_disp *disp = outp->disp;
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struct nvkm_subdev *subdev = &disp->engine.subdev;
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struct nvkm_bios *bios = subdev->device->bios;
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u32 lnkcmp;
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int ret;
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OUTP_DBG(outp, "programming link for %dx%02x", ior->dp.nr, ior->dp.bw);
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/* Intersect misc. capabilities of the OR and sink. */
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if (disp->engine.subdev.device->chipset < 0x110)
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outp->dp.dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED;
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if (disp->engine.subdev.device->chipset < 0xd0)
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outp->dp.dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
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if (AMPERE_IED_HACK(disp) && (lnkcmp = outp->dp.info.script[0])) {
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/* Execute BeforeLinkTraining script from DP Info table. */
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while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
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lnkcmp += 3;
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lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
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nvbios_init(&outp->disp->engine.subdev, lnkcmp,
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init.outp = &outp->info;
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init.or = ior->id;
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init.link = ior->asy.link;
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);
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}
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/* Set desired link configuration on the source. */
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if ((lnkcmp = outp->dp.info.lnkcmp)) {
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if (outp->dp.version < 0x30) {
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while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp))
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lnkcmp += 4;
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lnkcmp = nvbios_rd16(bios, lnkcmp + 2);
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} else {
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while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
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lnkcmp += 3;
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lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
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}
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nvbios_init(subdev, lnkcmp,
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init.outp = &outp->info;
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init.or = ior->id;
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init.link = ior->asy.link;
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);
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}
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ret = ior->func->dp->links(ior, outp->dp.aux);
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if (ret) {
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if (ret < 0) {
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OUTP_ERR(outp, "train failed with %d", ret);
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return ret;
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}
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return 0;
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}
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ior->func->dp->power(ior, ior->dp.nr);
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/* Attempt to train the link in this configuration. */
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return nvkm_dp_train_link(outp, rate);
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}
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static void
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nvkm_dp_train_fini(struct nvkm_outp *outp)
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{
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/* Execute AfterLinkTraining script from DP Info table. */
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nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[1],
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init.outp = &outp->info;
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init.or = outp->ior->id;
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init.link = outp->ior->asy.link;
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);
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}
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static void
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nvkm_dp_train_init(struct nvkm_outp *outp)
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{
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/* Execute EnableSpread/DisableSpread script from DP Info table. */
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if (outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) {
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nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[2],
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init.outp = &outp->info;
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init.or = outp->ior->id;
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init.link = outp->ior->asy.link;
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);
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} else {
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nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[3],
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init.outp = &outp->info;
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init.or = outp->ior->id;
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init.link = outp->ior->asy.link;
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);
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}
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if (!AMPERE_IED_HACK(outp->disp)) {
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/* Execute BeforeLinkTraining script from DP Info table. */
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nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[0],
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init.outp = &outp->info;
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init.or = outp->ior->id;
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init.link = outp->ior->asy.link;
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);
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}
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}
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static int
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nvkm_dp_train(struct nvkm_outp *outp, u32 dataKBps)
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{
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struct nvkm_ior *ior = outp->ior;
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int ret = -EINVAL, nr, rate;
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u8 pwr;
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/* Retraining link? Skip source configuration, it can mess up the active modeset. */
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if (atomic_read(&outp->dp.lt.done)) {
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for (rate = 0; rate < outp->dp.rates; rate++) {
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if (outp->dp.rate[rate].rate == ior->dp.bw * 27000)
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|
return nvkm_dp_train_link(outp, ret);
|
|
}
|
|
WARN_ON(1);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Ensure sink is not in a low-power state. */
|
|
if (!nvkm_rdaux(outp->dp.aux, DPCD_SC00, &pwr, 1)) {
|
|
if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) {
|
|
pwr &= ~DPCD_SC00_SET_POWER;
|
|
pwr |= DPCD_SC00_SET_POWER_D0;
|
|
nvkm_wraux(outp->dp.aux, DPCD_SC00, &pwr, 1);
|
|
}
|
|
}
|
|
|
|
ior->dp.mst = outp->dp.lt.mst;
|
|
ior->dp.ef = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;
|
|
ior->dp.nr = 0;
|
|
|
|
/* Link training. */
|
|
OUTP_DBG(outp, "training");
|
|
nvkm_dp_train_init(outp);
|
|
|
|
/* Validate and train at configuration requested (if any) on ACQUIRE. */
|
|
if (outp->dp.lt.nr) {
|
|
for (nr = outp->dp.links; ret < 0 && nr; nr >>= 1) {
|
|
for (rate = 0; nr == outp->dp.lt.nr && rate < outp->dp.rates; rate++) {
|
|
if (outp->dp.rate[rate].rate / 27000 == outp->dp.lt.bw) {
|
|
ior->dp.bw = outp->dp.rate[rate].rate / 27000;
|
|
ior->dp.nr = nr;
|
|
ret = nvkm_dp_train_links(outp, rate);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Otherwise, loop through all valid link configurations that support the data rate. */
|
|
for (nr = outp->dp.links; ret < 0 && nr; nr >>= 1) {
|
|
for (rate = 0; ret < 0 && rate < outp->dp.rates; rate++) {
|
|
if (outp->dp.rate[rate].rate * nr >= dataKBps || WARN_ON(!ior->dp.nr)) {
|
|
/* Program selected link configuration. */
|
|
ior->dp.bw = outp->dp.rate[rate].rate / 27000;
|
|
ior->dp.nr = nr;
|
|
ret = nvkm_dp_train_links(outp, rate);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Finish up. */
|
|
nvkm_dp_train_fini(outp);
|
|
if (ret < 0)
|
|
OUTP_ERR(outp, "training failed");
|
|
else
|
|
OUTP_DBG(outp, "training done");
|
|
atomic_set(&outp->dp.lt.done, 1);
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior)
|
|
{
|
|
/* Execute DisableLT script from DP Info Table. */
|
|
nvbios_init(&ior->disp->engine.subdev, outp->dp.info.script[4],
|
|
init.outp = &outp->info;
|
|
init.or = ior->id;
|
|
init.link = ior->arm.link;
|
|
);
|
|
}
|
|
|
|
static void
|
|
nvkm_dp_release(struct nvkm_outp *outp)
|
|
{
|
|
/* Prevent link from being retrained if sink sends an IRQ. */
|
|
atomic_set(&outp->dp.lt.done, 0);
|
|
outp->ior->dp.nr = 0;
|
|
}
|
|
|
|
static int
|
|
nvkm_dp_acquire(struct nvkm_outp *outp)
|
|
{
|
|
struct nvkm_ior *ior = outp->ior;
|
|
struct nvkm_head *head;
|
|
bool retrain = true;
|
|
u32 datakbps = 0;
|
|
u32 dataKBps;
|
|
u32 linkKBps;
|
|
u8 stat[3];
|
|
int ret, i;
|
|
|
|
mutex_lock(&outp->dp.mutex);
|
|
|
|
/* Check that link configuration meets current requirements. */
|
|
list_for_each_entry(head, &outp->disp->heads, head) {
|
|
if (ior->asy.head & (1 << head->id)) {
|
|
u32 khz = (head->asy.hz >> ior->asy.rgdiv) / 1000;
|
|
datakbps += khz * head->asy.or.depth;
|
|
}
|
|
}
|
|
|
|
linkKBps = ior->dp.bw * 27000 * ior->dp.nr;
|
|
dataKBps = DIV_ROUND_UP(datakbps, 8);
|
|
OUTP_DBG(outp, "data %d KB/s link %d KB/s mst %d->%d",
|
|
dataKBps, linkKBps, ior->dp.mst, outp->dp.lt.mst);
|
|
if (linkKBps < dataKBps || ior->dp.mst != outp->dp.lt.mst) {
|
|
OUTP_DBG(outp, "link requirements changed");
|
|
goto done;
|
|
}
|
|
|
|
/* Check that link is still trained. */
|
|
ret = nvkm_rdaux(outp->dp.aux, DPCD_LS02, stat, 3);
|
|
if (ret) {
|
|
OUTP_DBG(outp, "failed to read link status, assuming no sink");
|
|
goto done;
|
|
}
|
|
|
|
if (stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE) {
|
|
for (i = 0; i < ior->dp.nr; i++) {
|
|
u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f;
|
|
if (!(lane & DPCD_LS02_LANE0_CR_DONE) ||
|
|
!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
|
|
!(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) {
|
|
OUTP_DBG(outp, "lane %d not equalised", lane);
|
|
goto done;
|
|
}
|
|
}
|
|
retrain = false;
|
|
} else {
|
|
OUTP_DBG(outp, "no inter-lane alignment");
|
|
}
|
|
|
|
done:
|
|
if (retrain || !atomic_read(&outp->dp.lt.done))
|
|
ret = nvkm_dp_train(outp, dataKBps);
|
|
mutex_unlock(&outp->dp.mutex);
|
|
return ret;
|
|
}
|
|
|
|
static bool
|
|
nvkm_dp_enable_supported_link_rates(struct nvkm_outp *outp)
|
|
{
|
|
u8 sink_rates[DPCD_RC10_SUPPORTED_LINK_RATES__SIZE];
|
|
int i, j, k;
|
|
|
|
if (outp->conn->info.type != DCB_CONNECTOR_eDP ||
|
|
outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x13 ||
|
|
nvkm_rdaux(outp->dp.aux, DPCD_RC10_SUPPORTED_LINK_RATES(0),
|
|
sink_rates, sizeof(sink_rates)))
|
|
return false;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sink_rates); i += 2) {
|
|
const u32 rate = ((sink_rates[i + 1] << 8) | sink_rates[i]) * 200 / 10;
|
|
|
|
if (!rate || WARN_ON(outp->dp.rates == ARRAY_SIZE(outp->dp.rate)))
|
|
break;
|
|
|
|
if (rate > outp->info.dpconf.link_bw * 27000) {
|
|
OUTP_DBG(outp, "rate %d !outp", rate);
|
|
continue;
|
|
}
|
|
|
|
for (j = 0; j < outp->dp.rates; j++) {
|
|
if (rate > outp->dp.rate[j].rate) {
|
|
for (k = outp->dp.rates; k > j; k--)
|
|
outp->dp.rate[k] = outp->dp.rate[k - 1];
|
|
break;
|
|
}
|
|
}
|
|
|
|
outp->dp.rate[j].dpcd = i / 2;
|
|
outp->dp.rate[j].rate = rate;
|
|
outp->dp.rates++;
|
|
}
|
|
|
|
for (i = 0; i < outp->dp.rates; i++)
|
|
OUTP_DBG(outp, "link_rate[%d] = %d", outp->dp.rate[i].dpcd, outp->dp.rate[i].rate);
|
|
|
|
return outp->dp.rates != 0;
|
|
}
|
|
|
|
void
|
|
nvkm_dp_enable(struct nvkm_outp *outp, bool auxpwr)
|
|
{
|
|
struct nvkm_gpio *gpio = outp->disp->engine.subdev.device->gpio;
|
|
struct nvkm_i2c_aux *aux = outp->dp.aux;
|
|
|
|
if (auxpwr && !outp->dp.aux_pwr) {
|
|
/* eDP panels need powering on by us (if the VBIOS doesn't default it
|
|
* to on) before doing any AUX channel transactions. LVDS panel power
|
|
* is handled by the SOR itself, and not required for LVDS DDC.
|
|
*/
|
|
if (outp->conn->info.type == DCB_CONNECTOR_eDP) {
|
|
int power = nvkm_gpio_get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff);
|
|
if (power == 0) {
|
|
nvkm_gpio_set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1);
|
|
outp->dp.aux_pwr_pu = true;
|
|
}
|
|
|
|
/* We delay here unconditionally, even if already powered,
|
|
* because some laptop panels having a significant resume
|
|
* delay before the panel begins responding.
|
|
*
|
|
* This is likely a bit of a hack, but no better idea for
|
|
* handling this at the moment.
|
|
*/
|
|
msleep(300);
|
|
}
|
|
|
|
OUTP_DBG(outp, "aux power -> always");
|
|
nvkm_i2c_aux_monitor(aux, true);
|
|
outp->dp.aux_pwr = true;
|
|
|
|
/* Detect any LTTPRs before reading DPCD receiver caps. */
|
|
if (!nvkm_rdaux(aux, DPCD_LTTPR_REV, outp->dp.lttpr, sizeof(outp->dp.lttpr)) &&
|
|
outp->dp.lttpr[0] >= 0x14 && outp->dp.lttpr[2]) {
|
|
switch (outp->dp.lttpr[2]) {
|
|
case 0x80: outp->dp.lttprs = 1; break;
|
|
case 0x40: outp->dp.lttprs = 2; break;
|
|
case 0x20: outp->dp.lttprs = 3; break;
|
|
case 0x10: outp->dp.lttprs = 4; break;
|
|
case 0x08: outp->dp.lttprs = 5; break;
|
|
case 0x04: outp->dp.lttprs = 6; break;
|
|
case 0x02: outp->dp.lttprs = 7; break;
|
|
case 0x01: outp->dp.lttprs = 8; break;
|
|
default:
|
|
/* Unknown LTTPR count, we'll switch to transparent mode. */
|
|
WARN_ON(1);
|
|
outp->dp.lttprs = 0;
|
|
break;
|
|
}
|
|
} else {
|
|
/* No LTTPR support, or zero LTTPR count - don't touch it at all. */
|
|
memset(outp->dp.lttpr, 0x00, sizeof(outp->dp.lttpr));
|
|
}
|
|
|
|
if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, outp->dp.dpcd, sizeof(outp->dp.dpcd))) {
|
|
const u8 rates[] = { 0x1e, 0x14, 0x0a, 0x06, 0 };
|
|
const u8 *rate;
|
|
int rate_max;
|
|
|
|
outp->dp.rates = 0;
|
|
outp->dp.links = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT;
|
|
outp->dp.links = min(outp->dp.links, outp->info.dpconf.link_nr);
|
|
if (outp->dp.lttprs && outp->dp.lttpr[4])
|
|
outp->dp.links = min_t(int, outp->dp.links, outp->dp.lttpr[4]);
|
|
|
|
rate_max = outp->dp.dpcd[DPCD_RC01_MAX_LINK_RATE];
|
|
rate_max = min(rate_max, outp->info.dpconf.link_bw);
|
|
if (outp->dp.lttprs && outp->dp.lttpr[1])
|
|
rate_max = min_t(int, rate_max, outp->dp.lttpr[1]);
|
|
|
|
if (!nvkm_dp_enable_supported_link_rates(outp)) {
|
|
for (rate = rates; *rate; rate++) {
|
|
if (*rate > rate_max)
|
|
continue;
|
|
|
|
if (WARN_ON(outp->dp.rates == ARRAY_SIZE(outp->dp.rate)))
|
|
break;
|
|
|
|
outp->dp.rate[outp->dp.rates].dpcd = -1;
|
|
outp->dp.rate[outp->dp.rates].rate = *rate * 27000;
|
|
outp->dp.rates++;
|
|
}
|
|
}
|
|
}
|
|
} else
|
|
if (!auxpwr && outp->dp.aux_pwr) {
|
|
OUTP_DBG(outp, "aux power -> demand");
|
|
nvkm_i2c_aux_monitor(aux, false);
|
|
outp->dp.aux_pwr = false;
|
|
atomic_set(&outp->dp.lt.done, 0);
|
|
|
|
/* Restore eDP panel GPIO to its prior state if we changed it, as
|
|
* it could potentially interfere with other outputs.
|
|
*/
|
|
if (outp->conn->info.type == DCB_CONNECTOR_eDP) {
|
|
if (outp->dp.aux_pwr_pu) {
|
|
nvkm_gpio_set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 0);
|
|
outp->dp.aux_pwr_pu = false;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
nvkm_dp_fini(struct nvkm_outp *outp)
|
|
{
|
|
nvkm_dp_enable(outp, false);
|
|
}
|
|
|
|
static void
|
|
nvkm_dp_init(struct nvkm_outp *outp)
|
|
{
|
|
nvkm_dp_enable(outp, outp->dp.enabled);
|
|
}
|
|
|
|
static void *
|
|
nvkm_dp_dtor(struct nvkm_outp *outp)
|
|
{
|
|
return outp;
|
|
}
|
|
|
|
static const struct nvkm_outp_func
|
|
nvkm_dp_func = {
|
|
.dtor = nvkm_dp_dtor,
|
|
.init = nvkm_dp_init,
|
|
.fini = nvkm_dp_fini,
|
|
.acquire = nvkm_dp_acquire,
|
|
.release = nvkm_dp_release,
|
|
.disable = nvkm_dp_disable,
|
|
};
|
|
|
|
int
|
|
nvkm_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE, struct nvkm_outp **poutp)
|
|
{
|
|
struct nvkm_device *device = disp->engine.subdev.device;
|
|
struct nvkm_bios *bios = device->bios;
|
|
struct nvkm_i2c *i2c = device->i2c;
|
|
struct nvkm_outp *outp;
|
|
u8 hdr, cnt, len;
|
|
u32 data;
|
|
int ret;
|
|
|
|
ret = nvkm_outp_new_(&nvkm_dp_func, disp, index, dcbE, poutp);
|
|
outp = *poutp;
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (dcbE->location == 0)
|
|
outp->dp.aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_CCB(dcbE->i2c_index));
|
|
else
|
|
outp->dp.aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbE->extdev));
|
|
if (!outp->dp.aux) {
|
|
OUTP_ERR(outp, "no aux");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* bios data is not optional */
|
|
data = nvbios_dpout_match(bios, outp->info.hasht, outp->info.hashm,
|
|
&outp->dp.version, &hdr, &cnt, &len, &outp->dp.info);
|
|
if (!data) {
|
|
OUTP_ERR(outp, "no bios dp data");
|
|
return -EINVAL;
|
|
}
|
|
|
|
OUTP_DBG(outp, "bios dp %02x %02x %02x %02x", outp->dp.version, hdr, cnt, len);
|
|
|
|
mutex_init(&outp->dp.mutex);
|
|
atomic_set(&outp->dp.lt.done, 0);
|
|
return 0;
|
|
}
|