960 lines
28 KiB
C
960 lines
28 KiB
C
/*
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* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
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* VA Linux Systems Inc., Fremont, California.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Original Authors:
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* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
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*
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* Kernel port Author: Dave Airlie
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*/
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#ifndef RADEON_MODE_H
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#define RADEON_MODE_H
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#include <drm/display/drm_dp_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_fixed.h>
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#include <drm/drm_modeset_helper_vtables.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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struct radeon_bo;
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struct radeon_device;
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#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
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#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
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#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
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#define RADEON_MAX_HPD_PINS 7
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#define RADEON_MAX_CRTCS 6
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#define RADEON_MAX_AFMT_BLOCKS 7
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enum radeon_rmx_type {
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RMX_OFF,
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RMX_FULL,
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RMX_CENTER,
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RMX_ASPECT
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};
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enum radeon_tv_std {
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TV_STD_NTSC,
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TV_STD_PAL,
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TV_STD_PAL_M,
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TV_STD_PAL_60,
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TV_STD_NTSC_J,
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TV_STD_SCART_PAL,
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TV_STD_SECAM,
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TV_STD_PAL_CN,
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TV_STD_PAL_N,
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};
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enum radeon_underscan_type {
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UNDERSCAN_OFF,
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UNDERSCAN_ON,
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UNDERSCAN_AUTO,
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};
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enum radeon_hpd_id {
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RADEON_HPD_1 = 0,
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RADEON_HPD_2,
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RADEON_HPD_3,
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RADEON_HPD_4,
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RADEON_HPD_5,
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RADEON_HPD_6,
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RADEON_HPD_NONE = 0xff,
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};
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enum radeon_output_csc {
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RADEON_OUTPUT_CSC_BYPASS = 0,
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RADEON_OUTPUT_CSC_TVRGB = 1,
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RADEON_OUTPUT_CSC_YCBCR601 = 2,
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RADEON_OUTPUT_CSC_YCBCR709 = 3,
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};
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#define RADEON_MAX_I2C_BUS 16
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/* radeon gpio-based i2c
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* 1. "mask" reg and bits
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* grabs the gpio pins for software use
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* 0=not held 1=held
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* 2. "a" reg and bits
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* output pin value
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* 0=low 1=high
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* 3. "en" reg and bits
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* sets the pin direction
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* 0=input 1=output
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* 4. "y" reg and bits
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* input pin value
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* 0=low 1=high
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*/
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struct radeon_i2c_bus_rec {
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bool valid;
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/* id used by atom */
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uint8_t i2c_id;
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/* id used by atom */
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enum radeon_hpd_id hpd;
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/* can be used with hw i2c engine */
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bool hw_capable;
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/* uses multi-media i2c engine */
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bool mm_i2c;
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/* regs and bits */
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uint32_t mask_clk_reg;
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uint32_t mask_data_reg;
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uint32_t a_clk_reg;
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uint32_t a_data_reg;
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uint32_t en_clk_reg;
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uint32_t en_data_reg;
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uint32_t y_clk_reg;
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uint32_t y_data_reg;
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uint32_t mask_clk_mask;
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uint32_t mask_data_mask;
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uint32_t a_clk_mask;
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uint32_t a_data_mask;
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uint32_t en_clk_mask;
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uint32_t en_data_mask;
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uint32_t y_clk_mask;
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uint32_t y_data_mask;
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};
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struct radeon_tmds_pll {
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uint32_t freq;
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uint32_t value;
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};
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#define RADEON_MAX_BIOS_CONNECTOR 16
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/* pll flags */
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#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
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#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
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#define RADEON_PLL_USE_REF_DIV (1 << 2)
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#define RADEON_PLL_LEGACY (1 << 3)
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#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
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#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
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#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
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#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
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#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
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#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
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#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
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#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
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#define RADEON_PLL_USE_POST_DIV (1 << 12)
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#define RADEON_PLL_IS_LCD (1 << 13)
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#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
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struct radeon_pll {
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/* reference frequency */
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uint32_t reference_freq;
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/* fixed dividers */
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uint32_t reference_div;
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uint32_t post_div;
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/* pll in/out limits */
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uint32_t pll_in_min;
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uint32_t pll_in_max;
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uint32_t pll_out_min;
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uint32_t pll_out_max;
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uint32_t lcd_pll_out_min;
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uint32_t lcd_pll_out_max;
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uint32_t best_vco;
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/* divider limits */
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uint32_t min_ref_div;
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uint32_t max_ref_div;
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uint32_t min_post_div;
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uint32_t max_post_div;
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uint32_t min_feedback_div;
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uint32_t max_feedback_div;
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uint32_t min_frac_feedback_div;
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uint32_t max_frac_feedback_div;
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/* flags for the current clock */
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uint32_t flags;
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/* pll id */
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uint32_t id;
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};
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struct radeon_i2c_chan {
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struct i2c_adapter adapter;
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struct drm_device *dev;
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struct i2c_algo_bit_data bit;
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struct radeon_i2c_bus_rec rec;
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struct drm_dp_aux aux;
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bool has_aux;
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struct mutex mutex;
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};
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/* mostly for macs, but really any system without connector tables */
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enum radeon_connector_table {
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CT_NONE = 0,
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CT_GENERIC,
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CT_IBOOK,
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CT_POWERBOOK_EXTERNAL,
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CT_POWERBOOK_INTERNAL,
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CT_POWERBOOK_VGA,
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CT_MINI_EXTERNAL,
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CT_MINI_INTERNAL,
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CT_IMAC_G5_ISIGHT,
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CT_EMAC,
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CT_RN50_POWER,
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CT_MAC_X800,
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CT_MAC_G5_9600,
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CT_SAM440EP,
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CT_MAC_G4_SILVER
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};
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enum radeon_dvo_chip {
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DVO_SIL164,
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DVO_SIL1178,
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};
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struct radeon_fbdev;
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struct radeon_afmt {
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bool enabled;
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int offset;
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bool last_buffer_filled_status;
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int id;
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};
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struct radeon_mode_info {
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struct atom_context *atom_context;
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struct card_info *atom_card_info;
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enum radeon_connector_table connector_table;
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bool mode_config_initialized;
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struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
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struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
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/* DVI-I properties */
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struct drm_property *coherent_mode_property;
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/* DAC enable load detect */
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struct drm_property *load_detect_property;
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/* TV standard */
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struct drm_property *tv_std_property;
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/* legacy TMDS PLL detect */
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struct drm_property *tmds_pll_property;
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/* underscan */
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struct drm_property *underscan_property;
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struct drm_property *underscan_hborder_property;
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struct drm_property *underscan_vborder_property;
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/* audio */
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struct drm_property *audio_property;
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/* FMT dithering */
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struct drm_property *dither_property;
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/* Output CSC */
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struct drm_property *output_csc_property;
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/* hardcoded DFP edid from BIOS */
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struct edid *bios_hardcoded_edid;
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int bios_hardcoded_edid_size;
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/* pointer to fbdev info structure */
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struct radeon_fbdev *rfbdev;
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/* firmware flags */
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u16 firmware_flags;
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/* pointer to backlight encoder */
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struct radeon_encoder *bl_encoder;
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/* bitmask for active encoder frontends */
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uint32_t active_encoders;
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};
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#define RADEON_MAX_BL_LEVEL 0xFF
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struct radeon_backlight_privdata {
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struct radeon_encoder *encoder;
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uint8_t negative;
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};
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#define MAX_H_CODE_TIMING_LEN 32
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#define MAX_V_CODE_TIMING_LEN 32
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/* need to store these as reading
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back code tables is excessive */
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struct radeon_tv_regs {
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uint32_t tv_uv_adr;
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uint32_t timing_cntl;
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uint32_t hrestart;
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uint32_t vrestart;
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uint32_t frestart;
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uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
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uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
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};
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struct radeon_atom_ss {
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uint16_t percentage;
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uint16_t percentage_divider;
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uint8_t type;
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uint16_t step;
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uint8_t delay;
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uint8_t range;
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uint8_t refdiv;
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/* asic_ss */
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uint16_t rate;
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uint16_t amount;
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};
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enum radeon_flip_status {
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RADEON_FLIP_NONE,
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RADEON_FLIP_PENDING,
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RADEON_FLIP_SUBMITTED
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};
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struct radeon_crtc {
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struct drm_crtc base;
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int crtc_id;
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bool enabled;
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bool can_tile;
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bool cursor_out_of_bounds;
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uint32_t crtc_offset;
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struct drm_gem_object *cursor_bo;
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uint64_t cursor_addr;
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int cursor_x;
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int cursor_y;
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int cursor_hot_x;
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int cursor_hot_y;
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int cursor_width;
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int cursor_height;
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int max_cursor_width;
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int max_cursor_height;
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uint32_t legacy_display_base_addr;
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enum radeon_rmx_type rmx_type;
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u8 h_border;
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u8 v_border;
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fixed20_12 vsc;
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fixed20_12 hsc;
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struct drm_display_mode native_mode;
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int pll_id;
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/* page flipping */
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struct workqueue_struct *flip_queue;
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struct radeon_flip_work *flip_work;
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enum radeon_flip_status flip_status;
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/* pll sharing */
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struct radeon_atom_ss ss;
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bool ss_enabled;
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u32 adjusted_clock;
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int bpc;
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u32 pll_reference_div;
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u32 pll_post_div;
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u32 pll_flags;
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struct drm_encoder *encoder;
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struct drm_connector *connector;
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/* for dpm */
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u32 line_time;
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u32 wm_low;
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u32 wm_high;
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u32 lb_vblank_lead_lines;
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struct drm_display_mode hw_mode;
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enum radeon_output_csc output_csc;
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};
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struct radeon_encoder_primary_dac {
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/* legacy primary dac */
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uint32_t ps2_pdac_adj;
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};
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struct radeon_encoder_lvds {
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/* legacy lvds */
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uint16_t panel_vcc_delay;
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uint8_t panel_pwr_delay;
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uint8_t panel_digon_delay;
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uint8_t panel_blon_delay;
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uint16_t panel_ref_divider;
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uint8_t panel_post_divider;
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uint16_t panel_fb_divider;
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bool use_bios_dividers;
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uint32_t lvds_gen_cntl;
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/* panel mode */
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struct drm_display_mode native_mode;
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struct backlight_device *bl_dev;
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int dpms_mode;
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uint8_t backlight_level;
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};
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struct radeon_encoder_tv_dac {
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/* legacy tv dac */
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uint32_t ps2_tvdac_adj;
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uint32_t ntsc_tvdac_adj;
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uint32_t pal_tvdac_adj;
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int h_pos;
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int v_pos;
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int h_size;
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int supported_tv_stds;
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bool tv_on;
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enum radeon_tv_std tv_std;
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struct radeon_tv_regs tv;
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};
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struct radeon_encoder_int_tmds {
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/* legacy int tmds */
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struct radeon_tmds_pll tmds_pll[4];
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};
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struct radeon_encoder_ext_tmds {
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/* tmds over dvo */
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struct radeon_i2c_chan *i2c_bus;
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uint8_t slave_addr;
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enum radeon_dvo_chip dvo_chip;
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};
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/* spread spectrum */
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struct radeon_encoder_atom_dig {
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bool linkb;
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/* atom dig */
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bool coherent_mode;
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int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
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/* atom lvds/edp */
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uint32_t lcd_misc;
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uint16_t panel_pwr_delay;
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uint32_t lcd_ss_id;
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/* panel mode */
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struct drm_display_mode native_mode;
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struct backlight_device *bl_dev;
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int dpms_mode;
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uint8_t backlight_level;
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int panel_mode;
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struct radeon_afmt *afmt;
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struct r600_audio_pin *pin;
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};
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struct radeon_encoder_atom_dac {
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enum radeon_tv_std tv_std;
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};
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struct radeon_encoder {
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struct drm_encoder base;
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uint32_t encoder_enum;
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uint32_t encoder_id;
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uint32_t devices;
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uint32_t active_device;
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uint32_t flags;
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uint32_t pixel_clock;
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enum radeon_rmx_type rmx_type;
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enum radeon_underscan_type underscan_type;
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uint32_t underscan_hborder;
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uint32_t underscan_vborder;
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struct drm_display_mode native_mode;
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void *enc_priv;
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int audio_polling_active;
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bool is_ext_encoder;
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u16 caps;
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struct radeon_audio_funcs *audio;
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enum radeon_output_csc output_csc;
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bool can_mst;
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uint32_t offset;
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};
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struct radeon_connector_atom_dig {
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uint32_t igp_lane_info;
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/* displayport */
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u8 dpcd[DP_RECEIVER_CAP_SIZE];
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u8 dp_sink_type;
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int dp_clock;
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int dp_lane_count;
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bool edp_on;
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};
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struct radeon_gpio_rec {
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bool valid;
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u8 id;
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u32 reg;
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u32 mask;
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u32 shift;
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};
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struct radeon_hpd {
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enum radeon_hpd_id hpd;
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u8 plugged_state;
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struct radeon_gpio_rec gpio;
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};
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struct radeon_router {
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u32 router_id;
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struct radeon_i2c_bus_rec i2c_info;
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u8 i2c_addr;
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/* i2c mux */
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bool ddc_valid;
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u8 ddc_mux_type;
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u8 ddc_mux_control_pin;
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u8 ddc_mux_state;
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/* clock/data mux */
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bool cd_valid;
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u8 cd_mux_type;
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u8 cd_mux_control_pin;
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u8 cd_mux_state;
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};
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enum radeon_connector_audio {
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RADEON_AUDIO_DISABLE = 0,
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RADEON_AUDIO_ENABLE = 1,
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RADEON_AUDIO_AUTO = 2
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};
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enum radeon_connector_dither {
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RADEON_FMT_DITHER_DISABLE = 0,
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RADEON_FMT_DITHER_ENABLE = 1,
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};
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struct radeon_connector {
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struct drm_connector base;
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uint32_t connector_id;
|
|
uint32_t devices;
|
|
struct radeon_i2c_chan *ddc_bus;
|
|
/* some systems have an hdmi and vga port with a shared ddc line */
|
|
bool shared_ddc;
|
|
bool use_digital;
|
|
/* we need to mind the EDID between detect
|
|
and get modes due to analog/digital/tvencoder */
|
|
struct edid *edid;
|
|
void *con_priv;
|
|
bool dac_load_detect;
|
|
bool detected_by_load; /* if the connection status was determined by load */
|
|
bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
|
|
uint16_t connector_object_id;
|
|
struct radeon_hpd hpd;
|
|
struct radeon_router router;
|
|
struct radeon_i2c_chan *router_bus;
|
|
enum radeon_connector_audio audio;
|
|
enum radeon_connector_dither dither;
|
|
int pixelclock_for_modeset;
|
|
};
|
|
|
|
#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
|
|
((em) == ATOM_ENCODER_MODE_DP_MST))
|
|
|
|
struct atom_clock_dividers {
|
|
u32 post_div;
|
|
union {
|
|
struct {
|
|
#ifdef __BIG_ENDIAN
|
|
u32 reserved : 6;
|
|
u32 whole_fb_div : 12;
|
|
u32 frac_fb_div : 14;
|
|
#else
|
|
u32 frac_fb_div : 14;
|
|
u32 whole_fb_div : 12;
|
|
u32 reserved : 6;
|
|
#endif
|
|
};
|
|
u32 fb_div;
|
|
};
|
|
u32 ref_div;
|
|
bool enable_post_div;
|
|
bool enable_dithen;
|
|
u32 vco_mode;
|
|
u32 real_clock;
|
|
/* added for CI */
|
|
u32 post_divider;
|
|
u32 flags;
|
|
};
|
|
|
|
struct atom_mpll_param {
|
|
union {
|
|
struct {
|
|
#ifdef __BIG_ENDIAN
|
|
u32 reserved : 8;
|
|
u32 clkfrac : 12;
|
|
u32 clkf : 12;
|
|
#else
|
|
u32 clkf : 12;
|
|
u32 clkfrac : 12;
|
|
u32 reserved : 8;
|
|
#endif
|
|
};
|
|
u32 fb_div;
|
|
};
|
|
u32 post_div;
|
|
u32 bwcntl;
|
|
u32 dll_speed;
|
|
u32 vco_mode;
|
|
u32 yclk_sel;
|
|
u32 qdr;
|
|
u32 half_rate;
|
|
};
|
|
|
|
#define MEM_TYPE_GDDR5 0x50
|
|
#define MEM_TYPE_GDDR4 0x40
|
|
#define MEM_TYPE_GDDR3 0x30
|
|
#define MEM_TYPE_DDR2 0x20
|
|
#define MEM_TYPE_GDDR1 0x10
|
|
#define MEM_TYPE_DDR3 0xb0
|
|
#define MEM_TYPE_MASK 0xf0
|
|
|
|
struct atom_memory_info {
|
|
u8 mem_vendor;
|
|
u8 mem_type;
|
|
};
|
|
|
|
#define MAX_AC_TIMING_ENTRIES 16
|
|
|
|
struct atom_memory_clock_range_table
|
|
{
|
|
u8 num_entries;
|
|
u8 rsv[3];
|
|
u32 mclk[MAX_AC_TIMING_ENTRIES];
|
|
};
|
|
|
|
#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
|
|
#define VBIOS_MAX_AC_TIMING_ENTRIES 20
|
|
|
|
struct atom_mc_reg_entry {
|
|
u32 mclk_max;
|
|
u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
|
|
};
|
|
|
|
struct atom_mc_register_address {
|
|
u16 s1;
|
|
u8 pre_reg_data;
|
|
};
|
|
|
|
struct atom_mc_reg_table {
|
|
u8 last;
|
|
u8 num_entries;
|
|
struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
|
|
struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
|
|
};
|
|
|
|
#define MAX_VOLTAGE_ENTRIES 32
|
|
|
|
struct atom_voltage_table_entry
|
|
{
|
|
u16 value;
|
|
u32 smio_low;
|
|
};
|
|
|
|
struct atom_voltage_table
|
|
{
|
|
u32 count;
|
|
u32 mask_low;
|
|
u32 phase_delay;
|
|
struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
|
|
};
|
|
|
|
/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
|
|
#define DRM_SCANOUTPOS_VALID (1 << 0)
|
|
#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
|
|
#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
|
|
#define USE_REAL_VBLANKSTART (1 << 30)
|
|
#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
|
|
|
|
extern void
|
|
radeon_add_atom_connector(struct drm_device *dev,
|
|
uint32_t connector_id,
|
|
uint32_t supported_device,
|
|
int connector_type,
|
|
struct radeon_i2c_bus_rec *i2c_bus,
|
|
uint32_t igp_lane_info,
|
|
uint16_t connector_object_id,
|
|
struct radeon_hpd *hpd,
|
|
struct radeon_router *router);
|
|
extern void
|
|
radeon_add_legacy_connector(struct drm_device *dev,
|
|
uint32_t connector_id,
|
|
uint32_t supported_device,
|
|
int connector_type,
|
|
struct radeon_i2c_bus_rec *i2c_bus,
|
|
uint16_t connector_object_id,
|
|
struct radeon_hpd *hpd);
|
|
extern uint32_t
|
|
radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
|
|
uint8_t dac);
|
|
extern void radeon_link_encoder_connector(struct drm_device *dev);
|
|
|
|
extern enum radeon_tv_std
|
|
radeon_combios_get_tv_info(struct radeon_device *rdev);
|
|
extern enum radeon_tv_std
|
|
radeon_atombios_get_tv_info(struct radeon_device *rdev);
|
|
extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
|
|
u16 *vddc, u16 *vddci, u16 *mvdd);
|
|
|
|
extern void
|
|
radeon_combios_connected_scratch_regs(struct drm_connector *connector,
|
|
struct drm_encoder *encoder,
|
|
bool connected);
|
|
extern void
|
|
radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
|
|
struct drm_encoder *encoder,
|
|
bool connected);
|
|
|
|
extern struct drm_connector *
|
|
radeon_get_connector_for_encoder(struct drm_encoder *encoder);
|
|
extern struct drm_connector *
|
|
radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
|
|
extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
|
|
u32 pixel_clock);
|
|
|
|
extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
|
|
extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
|
|
extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
|
|
extern int radeon_get_monitor_bpc(struct drm_connector *connector);
|
|
|
|
extern struct edid *radeon_connector_edid(struct drm_connector *connector);
|
|
|
|
extern void radeon_connector_hotplug(struct drm_connector *connector);
|
|
extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
|
|
struct drm_display_mode *mode);
|
|
extern void radeon_dp_set_link_config(struct drm_connector *connector,
|
|
const struct drm_display_mode *mode);
|
|
extern void radeon_dp_link_train(struct drm_encoder *encoder,
|
|
struct drm_connector *connector);
|
|
extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
|
|
extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
|
|
extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
|
|
extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
|
|
struct drm_connector *connector);
|
|
extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
|
|
u8 power_state);
|
|
extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
|
|
extern ssize_t
|
|
radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
|
|
|
|
extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
|
|
extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
|
|
extern void radeon_atom_encoder_init(struct radeon_device *rdev);
|
|
extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
|
|
extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
|
|
int action, uint8_t lane_num,
|
|
uint8_t lane_set);
|
|
extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
|
|
int action, uint8_t lane_num,
|
|
uint8_t lane_set, int fe);
|
|
extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
|
|
extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
|
|
void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
|
|
|
|
extern void radeon_i2c_init(struct radeon_device *rdev);
|
|
extern void radeon_i2c_fini(struct radeon_device *rdev);
|
|
extern void radeon_combios_i2c_init(struct radeon_device *rdev);
|
|
extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
|
|
extern void radeon_i2c_add(struct radeon_device *rdev,
|
|
struct radeon_i2c_bus_rec *rec,
|
|
const char *name);
|
|
extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
|
|
struct radeon_i2c_bus_rec *i2c_bus);
|
|
extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
|
|
struct radeon_i2c_bus_rec *rec,
|
|
const char *name);
|
|
extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
|
|
extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
|
|
u8 slave_addr,
|
|
u8 addr,
|
|
u8 *val);
|
|
extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
|
|
u8 slave_addr,
|
|
u8 addr,
|
|
u8 val);
|
|
extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
|
|
extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
|
|
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
|
|
|
|
extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
|
|
struct radeon_atom_ss *ss,
|
|
int id);
|
|
extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
|
|
struct radeon_atom_ss *ss,
|
|
int id, u32 clock);
|
|
extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
|
|
u8 id);
|
|
|
|
extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
|
|
uint64_t freq,
|
|
uint32_t *dot_clock_p,
|
|
uint32_t *fb_div_p,
|
|
uint32_t *frac_fb_div_p,
|
|
uint32_t *ref_div_p,
|
|
uint32_t *post_div_p);
|
|
|
|
extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
|
|
u32 freq,
|
|
u32 *dot_clock_p,
|
|
u32 *fb_div_p,
|
|
u32 *frac_fb_div_p,
|
|
u32 *ref_div_p,
|
|
u32 *post_div_p);
|
|
|
|
extern void radeon_setup_encoder_clones(struct drm_device *dev);
|
|
|
|
struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
|
|
struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
|
|
struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
|
|
struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
|
|
struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
|
|
extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
|
|
extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
|
|
extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
|
|
extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
|
|
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
|
|
extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
|
|
|
|
extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
|
|
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
|
struct drm_framebuffer *old_fb);
|
|
extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
int x, int y,
|
|
enum mode_set_atomic state);
|
|
extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode,
|
|
int x, int y,
|
|
struct drm_framebuffer *old_fb);
|
|
extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
|
|
|
|
extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
|
struct drm_framebuffer *old_fb);
|
|
extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
int x, int y,
|
|
enum mode_set_atomic state);
|
|
extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
int x, int y, int atomic);
|
|
extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
|
|
struct drm_file *file_priv,
|
|
uint32_t handle,
|
|
uint32_t width,
|
|
uint32_t height,
|
|
int32_t hot_x,
|
|
int32_t hot_y);
|
|
extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
|
|
int x, int y);
|
|
extern void radeon_cursor_reset(struct drm_crtc *crtc);
|
|
|
|
extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
|
|
unsigned int flags, int *vpos, int *hpos,
|
|
ktime_t *stime, ktime_t *etime,
|
|
const struct drm_display_mode *mode);
|
|
|
|
extern bool
|
|
radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
|
|
int *vpos, int *hpos,
|
|
ktime_t *stime, ktime_t *etime,
|
|
const struct drm_display_mode *mode);
|
|
|
|
extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
|
|
extern struct edid *
|
|
radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
|
|
extern bool radeon_atom_get_clock_info(struct drm_device *dev);
|
|
extern bool radeon_combios_get_clock_info(struct drm_device *dev);
|
|
extern struct radeon_encoder_atom_dig *
|
|
radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
|
|
extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
|
|
struct radeon_encoder_int_tmds *tmds);
|
|
extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
|
|
struct radeon_encoder_int_tmds *tmds);
|
|
extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
|
|
struct radeon_encoder_int_tmds *tmds);
|
|
extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
|
|
struct radeon_encoder_ext_tmds *tmds);
|
|
extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
|
|
struct radeon_encoder_ext_tmds *tmds);
|
|
extern struct radeon_encoder_primary_dac *
|
|
radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
|
|
extern struct radeon_encoder_tv_dac *
|
|
radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
|
|
extern struct radeon_encoder_lvds *
|
|
radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
|
|
extern struct radeon_encoder_tv_dac *
|
|
radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
|
|
extern struct radeon_encoder_primary_dac *
|
|
radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
|
|
extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
|
|
extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
|
|
extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
|
|
extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
|
|
extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
|
|
extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
|
|
extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
|
|
extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
|
|
extern void
|
|
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
|
|
extern void
|
|
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
|
|
extern void
|
|
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
|
|
extern void
|
|
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
|
|
int radeon_framebuffer_init(struct drm_device *dev,
|
|
struct drm_framebuffer *rfb,
|
|
const struct drm_mode_fb_cmd2 *mode_cmd,
|
|
struct drm_gem_object *obj);
|
|
|
|
int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
|
|
bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
|
|
bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
|
|
void radeon_atombios_init_crtc(struct drm_device *dev,
|
|
struct radeon_crtc *radeon_crtc);
|
|
void radeon_legacy_init_crtc(struct drm_device *dev,
|
|
struct radeon_crtc *radeon_crtc);
|
|
|
|
void radeon_get_clock_info(struct drm_device *dev);
|
|
|
|
extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
|
|
extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
|
|
|
|
void radeon_enc_destroy(struct drm_encoder *encoder);
|
|
void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
|
|
void radeon_combios_asic_init(struct drm_device *dev);
|
|
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode);
|
|
void radeon_panel_mode_fixup(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode);
|
|
void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
|
|
|
|
/* legacy tv */
|
|
void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
|
|
uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
|
|
uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
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void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
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uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
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uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
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void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
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uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
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uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
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void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode);
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/* fmt blocks */
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void avivo_program_fmt(struct drm_encoder *encoder);
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void dce3_program_fmt(struct drm_encoder *encoder);
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void dce4_program_fmt(struct drm_encoder *encoder);
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void dce8_program_fmt(struct drm_encoder *encoder);
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/* fbdev layer */
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int radeon_fbdev_init(struct radeon_device *rdev);
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void radeon_fbdev_fini(struct radeon_device *rdev);
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void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
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bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
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void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
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void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
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int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
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int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
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void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
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#endif
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