255 lines
6.6 KiB
C
255 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __HWMON_NCT6775_H__
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#define __HWMON_NCT6775_H__
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#include <linux/types.h>
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enum kinds { nct6106, nct6116, nct6775, nct6776, nct6779, nct6791, nct6792,
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nct6793, nct6795, nct6796, nct6797, nct6798 };
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enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
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#define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
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#define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
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#define NUM_TSI_TEMP 8 /* Max number of TSI temp register pairs */
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#define NUM_REG_ALARM 7 /* Max number of alarm registers */
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#define NUM_REG_BEEP 5 /* Max number of beep registers */
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#define NUM_FAN 7
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struct nct6775_data {
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int addr; /* IO base of hw monitor block */
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int sioreg; /* SIO register address */
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enum kinds kind;
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const char *name;
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const struct attribute_group *groups[7];
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u8 num_groups;
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u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
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* 3=temp_crit, 4=temp_lcrit
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*/
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u8 temp_src[NUM_TEMP];
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u16 reg_temp_config[NUM_TEMP];
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const char * const *temp_label;
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u32 temp_mask;
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u32 virt_temp_mask;
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u16 REG_CONFIG;
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u16 REG_VBAT;
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u16 REG_DIODE;
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u8 DIODE_MASK;
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const s8 *ALARM_BITS;
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const s8 *BEEP_BITS;
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const u16 *REG_VIN;
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const u16 *REG_IN_MINMAX[2];
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const u16 *REG_TARGET;
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const u16 *REG_FAN;
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const u16 *REG_FAN_MODE;
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const u16 *REG_FAN_MIN;
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const u16 *REG_FAN_PULSES;
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const u16 *FAN_PULSE_SHIFT;
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const u16 *REG_FAN_TIME[3];
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const u16 *REG_TOLERANCE_H;
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const u8 *REG_PWM_MODE;
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const u8 *PWM_MODE_MASK;
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const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
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* [3]=pwm_max, [4]=pwm_step,
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* [5]=weight_duty_step, [6]=weight_duty_base
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*/
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const u16 *REG_PWM_READ;
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const u16 *REG_CRITICAL_PWM_ENABLE;
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u8 CRITICAL_PWM_ENABLE_MASK;
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const u16 *REG_CRITICAL_PWM;
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const u16 *REG_AUTO_TEMP;
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const u16 *REG_AUTO_PWM;
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const u16 *REG_CRITICAL_TEMP;
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const u16 *REG_CRITICAL_TEMP_TOLERANCE;
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const u16 *REG_TEMP_SOURCE; /* temp register sources */
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const u16 *REG_TEMP_SEL;
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const u16 *REG_WEIGHT_TEMP_SEL;
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const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
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const u16 *REG_TEMP_OFFSET;
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const u16 *REG_ALARM;
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const u16 *REG_BEEP;
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const u16 *REG_TSI_TEMP;
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unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
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unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
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struct mutex update_lock;
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bool valid; /* true if following fields are valid */
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unsigned long last_updated; /* In jiffies */
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/* Register values */
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u8 bank; /* current register bank */
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u8 in_num; /* number of in inputs we have */
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u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
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unsigned int rpm[NUM_FAN];
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u16 fan_min[NUM_FAN];
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u8 fan_pulses[NUM_FAN];
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u8 fan_div[NUM_FAN];
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u8 has_pwm;
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u8 has_fan; /* some fan inputs can be disabled */
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u8 has_fan_min; /* some fans don't have min register */
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bool has_fan_div;
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u8 num_temp_alarms; /* 2, 3, or 6 */
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u8 num_temp_beeps; /* 2, 3, or 6 */
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u8 temp_fixed_num; /* 3 or 6 */
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u8 temp_type[NUM_TEMP_FIXED];
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s8 temp_offset[NUM_TEMP_FIXED];
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s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
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* 3=temp_crit, 4=temp_lcrit
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*/
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s16 tsi_temp[NUM_TSI_TEMP];
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u64 alarms;
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u64 beeps;
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u8 pwm_num; /* number of pwm */
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u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
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* 1->PWM variable duty cycle
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*/
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enum pwm_enable pwm_enable[NUM_FAN];
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/* 0->off
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* 1->manual
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* 2->thermal cruise mode (also called SmartFan I)
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* 3->fan speed cruise mode
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* 4->SmartFan III
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* 5->enhanced variable thermal cruise (SmartFan IV)
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*/
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u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
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* [3]=pwm_max, [4]=pwm_step,
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* [5]=weight_duty_step, [6]=weight_duty_base
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*/
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u8 target_temp[NUM_FAN];
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u8 target_temp_mask;
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u32 target_speed[NUM_FAN];
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u32 target_speed_tolerance[NUM_FAN];
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u8 speed_tolerance_limit;
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u8 temp_tolerance[2][NUM_FAN];
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u8 tolerance_mask;
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u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
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/* Automatic fan speed control registers */
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int auto_pwm_num;
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u8 auto_pwm[NUM_FAN][7];
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u8 auto_temp[NUM_FAN][7];
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u8 pwm_temp_sel[NUM_FAN];
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u8 pwm_weight_temp_sel[NUM_FAN];
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u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
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* 2->temp_base
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*/
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u8 vid;
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u8 vrm;
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bool have_vid;
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u16 have_temp;
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u16 have_temp_fixed;
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u16 have_tsi_temp;
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u16 have_in;
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/* Remember extra register values over suspend/resume */
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u8 vbat;
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u8 fandiv1;
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u8 fandiv2;
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u8 sio_reg_enable;
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struct regmap *regmap;
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bool read_only;
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/* driver-specific (platform, i2c) initialization hook and data */
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int (*driver_init)(struct nct6775_data *data);
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void *driver_data;
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};
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static inline int nct6775_read_value(struct nct6775_data *data, u16 reg, u16 *value)
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{
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unsigned int tmp;
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int ret = regmap_read(data->regmap, reg, &tmp);
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if (!ret)
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*value = tmp;
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return ret;
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}
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static inline int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
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{
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return regmap_write(data->regmap, reg, value);
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}
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struct nct6775_data *nct6775_update_device(struct device *dev);
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bool nct6775_reg_is_word_sized(struct nct6775_data *data, u16 reg);
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int nct6775_probe(struct device *dev, struct nct6775_data *data,
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const struct regmap_config *regmapcfg);
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ssize_t nct6775_show_alarm(struct device *dev, struct device_attribute *attr, char *buf);
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ssize_t nct6775_show_beep(struct device *dev, struct device_attribute *attr, char *buf);
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ssize_t nct6775_store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
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size_t count);
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static inline int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
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{
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if (!nct6775_reg_is_word_sized(data, reg))
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value >>= 8;
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return nct6775_write_value(data, reg, value);
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}
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static inline umode_t nct6775_attr_mode(struct nct6775_data *data, struct attribute *attr)
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{
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return data->read_only ? (attr->mode & ~0222) : attr->mode;
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}
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static inline int
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nct6775_add_attr_group(struct nct6775_data *data, const struct attribute_group *group)
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{
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/* Need to leave a NULL terminator at the end of data->groups */
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if (data->num_groups == ARRAY_SIZE(data->groups) - 1)
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return -ENOBUFS;
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data->groups[data->num_groups++] = group;
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return 0;
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}
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#define NCT6775_REG_BANK 0x4E
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#define NCT6775_REG_CONFIG 0x40
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#define NCT6775_REG_FANDIV1 0x506
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#define NCT6775_REG_FANDIV2 0x507
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#define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
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#define FAN_ALARM_BASE 16
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#define TEMP_ALARM_BASE 24
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#define INTRUSION_ALARM_BASE 30
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#define BEEP_ENABLE_BASE 15
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/*
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* Not currently used:
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* REG_MAN_ID has the value 0x5ca3 for all supported chips.
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* REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
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* REG_MAN_ID is at port 0x4f
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* REG_CHIP_ID is at port 0x58
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*/
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#endif /* __HWMON_NCT6775_H__ */
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