63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CORESIGHT_CORESIGHT_TPDM_H
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#define _CORESIGHT_CORESIGHT_TPDM_H
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/* The max number of the datasets that TPDM supports */
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#define TPDM_DATASETS 7
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/* DSB Subunit Registers */
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#define TPDM_DSB_CR (0x780)
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/* Enable bit for DSB subunit */
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#define TPDM_DSB_CR_ENA BIT(0)
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/* TPDM integration test registers */
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#define TPDM_ITATBCNTRL (0xEF0)
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#define TPDM_ITCNTRL (0xF00)
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/* Register value for integration test */
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#define ATBCNTRL_VAL_32 0xC00F1409
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#define ATBCNTRL_VAL_64 0xC01F1409
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/*
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* Number of cycles to write value when
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* integration test.
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*/
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#define INTEGRATION_TEST_CYCLE 10
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/**
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* The bits of PERIPHIDR0 register.
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* The fields [6:0] of PERIPHIDR0 are used to determine what
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* interfaces and subunits are present on a given TPDM.
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*
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* PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
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* PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
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*/
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#define TPDM_PIDR0_DS_IMPDEF BIT(0)
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#define TPDM_PIDR0_DS_DSB BIT(1)
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/**
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* struct tpdm_drvdata - specifics associated to an TPDM component
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* @base: memory mapped base address for this component.
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* @dev: The device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @spinlock: lock for the drvdata value.
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* @enable: enable status of the component.
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* @datasets: The datasets types present of the TPDM.
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*/
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struct tpdm_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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bool enable;
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unsigned long datasets;
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};
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#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
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