1155 lines
28 KiB
C
1155 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* NETJet mISDN driver
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*
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* Author Karsten Keil <keil@isdn4linux.de>
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*
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* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/mISDNhw.h>
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#include <linux/slab.h>
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#include "ipac.h"
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#include "iohelper.h"
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#include "netjet.h"
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#include "isdnhdlc.h"
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#define NETJET_REV "2.0"
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enum nj_types {
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NETJET_S_TJ300,
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NETJET_S_TJ320,
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ENTERNOW__TJ320,
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};
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struct tiger_dma {
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size_t size;
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u32 *start;
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int idx;
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u32 dmastart;
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u32 dmairq;
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u32 dmaend;
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u32 dmacur;
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};
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struct tiger_hw;
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struct tiger_ch {
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struct bchannel bch;
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struct tiger_hw *nj;
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int idx;
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int free;
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int lastrx;
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u16 rxstate;
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u16 txstate;
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struct isdnhdlc_vars hsend;
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struct isdnhdlc_vars hrecv;
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u8 *hsbuf;
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u8 *hrbuf;
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};
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#define TX_INIT 0x0001
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#define TX_IDLE 0x0002
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#define TX_RUN 0x0004
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#define TX_UNDERRUN 0x0100
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#define RX_OVERRUN 0x0100
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#define LOG_SIZE 64
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struct tiger_hw {
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struct list_head list;
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struct pci_dev *pdev;
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char name[MISDN_MAX_IDLEN];
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enum nj_types typ;
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int irq;
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u32 irqcnt;
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u32 base;
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size_t base_s;
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dma_addr_t dma;
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void *dma_p;
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spinlock_t lock; /* lock HW */
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struct isac_hw isac;
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struct tiger_dma send;
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struct tiger_dma recv;
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struct tiger_ch bc[2];
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u8 ctrlreg;
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u8 dmactrl;
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u8 auxd;
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u8 last_is0;
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u8 irqmask0;
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char log[LOG_SIZE];
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};
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static LIST_HEAD(Cards);
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static DEFINE_RWLOCK(card_lock); /* protect Cards */
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static u32 debug;
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static int nj_cnt;
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static void
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_set_debug(struct tiger_hw *card)
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{
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card->isac.dch.debug = debug;
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card->bc[0].bch.debug = debug;
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card->bc[1].bch.debug = debug;
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}
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static int
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set_debug(const char *val, const struct kernel_param *kp)
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{
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int ret;
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struct tiger_hw *card;
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ret = param_set_uint(val, kp);
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if (!ret) {
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read_lock(&card_lock);
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list_for_each_entry(card, &Cards, list)
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_set_debug(card);
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read_unlock(&card_lock);
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}
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return ret;
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}
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MODULE_AUTHOR("Karsten Keil");
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION(NETJET_REV);
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module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(debug, "Netjet debug mask");
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static void
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nj_disable_hwirq(struct tiger_hw *card)
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{
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outb(0, card->base + NJ_IRQMASK0);
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outb(0, card->base + NJ_IRQMASK1);
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}
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static u8
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ReadISAC_nj(void *p, u8 offset)
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{
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struct tiger_hw *card = p;
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u8 ret;
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card->auxd &= 0xfc;
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card->auxd |= (offset >> 4) & 3;
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outb(card->auxd, card->base + NJ_AUXDATA);
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ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
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return ret;
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}
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static void
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WriteISAC_nj(void *p, u8 offset, u8 value)
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{
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struct tiger_hw *card = p;
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card->auxd &= 0xfc;
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card->auxd |= (offset >> 4) & 3;
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outb(card->auxd, card->base + NJ_AUXDATA);
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outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
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}
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static void
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ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
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{
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struct tiger_hw *card = p;
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card->auxd &= 0xfc;
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outb(card->auxd, card->base + NJ_AUXDATA);
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insb(card->base + NJ_ISAC_OFF, data, size);
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}
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static void
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WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
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{
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struct tiger_hw *card = p;
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card->auxd &= 0xfc;
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outb(card->auxd, card->base + NJ_AUXDATA);
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outsb(card->base + NJ_ISAC_OFF, data, size);
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}
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static void
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fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill)
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{
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struct tiger_hw *card = bc->bch.hw;
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u32 mask = 0xff, val;
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pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name,
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bc->bch.nr, fill, cnt, idx, card->send.idx);
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if (bc->bch.nr & 2) {
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fill <<= 8;
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mask <<= 8;
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}
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mask ^= 0xffffffff;
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while (cnt--) {
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val = card->send.start[idx];
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val &= mask;
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val |= fill;
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card->send.start[idx++] = val;
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if (idx >= card->send.size)
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idx = 0;
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}
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}
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static int
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mode_tiger(struct tiger_ch *bc, u32 protocol)
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{
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struct tiger_hw *card = bc->bch.hw;
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pr_debug("%s: B%1d protocol %x-->%x\n", card->name,
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bc->bch.nr, bc->bch.state, protocol);
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switch (protocol) {
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case ISDN_P_NONE:
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if (bc->bch.state == ISDN_P_NONE)
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break;
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fill_mem(bc, 0, card->send.size, 0xff);
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bc->bch.state = protocol;
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/* only stop dma and interrupts if both channels NULL */
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if ((card->bc[0].bch.state == ISDN_P_NONE) &&
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(card->bc[1].bch.state == ISDN_P_NONE)) {
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card->dmactrl = 0;
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outb(card->dmactrl, card->base + NJ_DMACTRL);
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outb(0, card->base + NJ_IRQMASK0);
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}
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test_and_clear_bit(FLG_HDLC, &bc->bch.Flags);
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test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags);
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bc->txstate = 0;
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bc->rxstate = 0;
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bc->lastrx = -1;
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break;
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case ISDN_P_B_RAW:
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test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags);
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bc->bch.state = protocol;
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bc->idx = 0;
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bc->free = card->send.size / 2;
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bc->rxstate = 0;
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bc->txstate = TX_INIT | TX_IDLE;
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bc->lastrx = -1;
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if (!card->dmactrl) {
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card->dmactrl = 1;
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outb(card->dmactrl, card->base + NJ_DMACTRL);
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outb(0x0f, card->base + NJ_IRQMASK0);
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}
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break;
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case ISDN_P_B_HDLC:
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test_and_set_bit(FLG_HDLC, &bc->bch.Flags);
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bc->bch.state = protocol;
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bc->idx = 0;
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bc->free = card->send.size / 2;
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bc->rxstate = 0;
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bc->txstate = TX_INIT | TX_IDLE;
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isdnhdlc_rcv_init(&bc->hrecv, 0);
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isdnhdlc_out_init(&bc->hsend, 0);
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bc->lastrx = -1;
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if (!card->dmactrl) {
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card->dmactrl = 1;
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outb(card->dmactrl, card->base + NJ_DMACTRL);
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outb(0x0f, card->base + NJ_IRQMASK0);
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}
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break;
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default:
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pr_info("%s: %s protocol %x not handled\n", card->name,
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__func__, protocol);
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return -ENOPROTOOPT;
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}
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card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR);
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card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR);
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card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
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card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
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pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n",
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card->name, __func__,
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inb(card->base + NJ_DMACTRL),
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inb(card->base + NJ_IRQMASK0),
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inb(card->base + NJ_IRQSTAT0),
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card->send.idx,
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card->recv.idx);
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return 0;
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}
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static void
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nj_reset(struct tiger_hw *card)
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{
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outb(0xff, card->base + NJ_CTRL); /* Reset On */
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mdelay(1);
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/* now edge triggered for TJ320 GE 13/07/00 */
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/* see comment in IRQ function */
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if (card->typ == NETJET_S_TJ320) /* TJ320 */
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card->ctrlreg = 0x40; /* Reset Off and status read clear */
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else
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card->ctrlreg = 0x00; /* Reset Off and status read clear */
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outb(card->ctrlreg, card->base + NJ_CTRL);
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mdelay(10);
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/* configure AUX pins (all output except ISAC IRQ pin) */
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card->auxd = 0;
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card->dmactrl = 0;
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outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL);
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outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1);
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outb(card->auxd, card->base + NJ_AUXDATA);
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}
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static int
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inittiger(struct tiger_hw *card)
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{
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int i;
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card->dma_p = dma_alloc_coherent(&card->pdev->dev, NJ_DMA_SIZE,
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&card->dma, GFP_ATOMIC);
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if (!card->dma_p) {
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pr_info("%s: No DMA memory\n", card->name);
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return -ENOMEM;
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}
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if ((u64)card->dma > 0xffffffff) {
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pr_info("%s: DMA outside 32 bit\n", card->name);
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return -ENOMEM;
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}
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for (i = 0; i < 2; i++) {
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card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC);
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if (!card->bc[i].hsbuf) {
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pr_info("%s: no B%d send buffer\n", card->name, i + 1);
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return -ENOMEM;
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}
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card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC);
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if (!card->bc[i].hrbuf) {
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pr_info("%s: no B%d recv buffer\n", card->name, i + 1);
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return -ENOMEM;
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}
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}
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memset(card->dma_p, 0xff, NJ_DMA_SIZE);
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card->send.start = card->dma_p;
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card->send.dmastart = (u32)card->dma;
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card->send.dmaend = card->send.dmastart +
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(4 * (NJ_DMA_TXSIZE - 1));
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card->send.dmairq = card->send.dmastart +
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(4 * ((NJ_DMA_TXSIZE / 2) - 1));
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card->send.size = NJ_DMA_TXSIZE;
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if (debug & DEBUG_HW)
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pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p"
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" size %zu u32\n", card->name,
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card->send.dmastart, card->send.dmairq,
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card->send.dmaend, card->send.start, card->send.size);
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outl(card->send.dmastart, card->base + NJ_DMA_READ_START);
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outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ);
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outl(card->send.dmaend, card->base + NJ_DMA_READ_END);
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card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2);
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card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2);
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card->recv.dmaend = card->recv.dmastart +
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(4 * (NJ_DMA_RXSIZE - 1));
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card->recv.dmairq = card->recv.dmastart +
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(4 * ((NJ_DMA_RXSIZE / 2) - 1));
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card->recv.size = NJ_DMA_RXSIZE;
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if (debug & DEBUG_HW)
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pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p"
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" size %zu u32\n", card->name,
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card->recv.dmastart, card->recv.dmairq,
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card->recv.dmaend, card->recv.start, card->recv.size);
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outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START);
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outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ);
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outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END);
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return 0;
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}
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static void
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read_dma(struct tiger_ch *bc, u32 idx, int cnt)
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{
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struct tiger_hw *card = bc->bch.hw;
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int i, stat;
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u32 val;
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u8 *p, *pn;
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if (bc->lastrx == idx) {
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bc->rxstate |= RX_OVERRUN;
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pr_info("%s: B%1d overrun at idx %d\n", card->name,
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bc->bch.nr, idx);
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}
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bc->lastrx = idx;
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if (test_bit(FLG_RX_OFF, &bc->bch.Flags)) {
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bc->bch.dropcnt += cnt;
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return;
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}
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stat = bchannel_get_rxbuf(&bc->bch, cnt);
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/* only transparent use the count here, HDLC overun is detected later */
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if (stat == -ENOMEM) {
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pr_warn("%s.B%d: No memory for %d bytes\n",
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card->name, bc->bch.nr, cnt);
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return;
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}
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if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags))
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p = skb_put(bc->bch.rx_skb, cnt);
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else
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p = bc->hrbuf;
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for (i = 0; i < cnt; i++) {
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val = card->recv.start[idx++];
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if (bc->bch.nr & 2)
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val >>= 8;
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if (idx >= card->recv.size)
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idx = 0;
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p[i] = val & 0xff;
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}
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if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) {
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recv_Bchannel(&bc->bch, 0, false);
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return;
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}
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pn = bc->hrbuf;
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while (cnt > 0) {
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stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i,
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bc->bch.rx_skb->data, bc->bch.maxlen);
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if (stat > 0) { /* valid frame received */
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p = skb_put(bc->bch.rx_skb, stat);
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if (debug & DEBUG_HW_BFIFO) {
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snprintf(card->log, LOG_SIZE,
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"B%1d-recv %s %d ", bc->bch.nr,
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card->name, stat);
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print_hex_dump_bytes(card->log,
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DUMP_PREFIX_OFFSET, p,
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stat);
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}
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recv_Bchannel(&bc->bch, 0, false);
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stat = bchannel_get_rxbuf(&bc->bch, bc->bch.maxlen);
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if (stat < 0) {
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pr_warn("%s.B%d: No memory for %d bytes\n",
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card->name, bc->bch.nr, cnt);
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return;
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}
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} else if (stat == -HDLC_CRC_ERROR) {
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pr_info("%s: B%1d receive frame CRC error\n",
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card->name, bc->bch.nr);
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} else if (stat == -HDLC_FRAMING_ERROR) {
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pr_info("%s: B%1d receive framing error\n",
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card->name, bc->bch.nr);
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} else if (stat == -HDLC_LENGTH_ERROR) {
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pr_info("%s: B%1d receive frame too long (> %d)\n",
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card->name, bc->bch.nr, bc->bch.maxlen);
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}
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pn += i;
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cnt -= i;
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}
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}
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static void
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recv_tiger(struct tiger_hw *card, u8 irq_stat)
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{
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u32 idx;
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int cnt = card->recv.size / 2;
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/* Note receive is via the WRITE DMA channel */
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card->last_is0 &= ~NJ_IRQM0_WR_MASK;
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card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK);
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if (irq_stat & NJ_IRQM0_WR_END)
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idx = cnt - 1;
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else
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idx = card->recv.size - 1;
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if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags))
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read_dma(&card->bc[0], idx, cnt);
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if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags))
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read_dma(&card->bc[1], idx, cnt);
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}
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/* sync with current DMA address at start or after exception */
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static void
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resync(struct tiger_ch *bc, struct tiger_hw *card)
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{
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card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
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card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
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if (bc->free > card->send.size / 2)
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bc->free = card->send.size / 2;
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/* currently we simple sync to the next complete free area
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* this hast the advantage that we have always maximum time to
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* handle TX irq
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*/
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if (card->send.idx < ((card->send.size / 2) - 1))
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bc->idx = (card->recv.size / 2) - 1;
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else
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bc->idx = card->recv.size - 1;
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bc->txstate = TX_RUN;
|
|
pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name,
|
|
__func__, bc->bch.nr, bc->free, bc->idx, card->send.idx);
|
|
}
|
|
|
|
static int bc_next_frame(struct tiger_ch *);
|
|
|
|
static void
|
|
fill_hdlc_flag(struct tiger_ch *bc)
|
|
{
|
|
struct tiger_hw *card = bc->bch.hw;
|
|
int count, i;
|
|
u32 m, v;
|
|
u8 *p;
|
|
|
|
if (bc->free == 0)
|
|
return;
|
|
pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name,
|
|
__func__, bc->bch.nr, bc->free, bc->txstate,
|
|
bc->idx, card->send.idx);
|
|
if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
|
|
resync(bc, card);
|
|
count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i,
|
|
bc->hsbuf, bc->free);
|
|
pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name,
|
|
bc->bch.nr, count);
|
|
bc->free -= count;
|
|
p = bc->hsbuf;
|
|
m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
|
|
for (i = 0; i < count; i++) {
|
|
if (bc->idx >= card->send.size)
|
|
bc->idx = 0;
|
|
v = card->send.start[bc->idx];
|
|
v &= m;
|
|
v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
|
|
card->send.start[bc->idx++] = v;
|
|
}
|
|
if (debug & DEBUG_HW_BFIFO) {
|
|
snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
|
|
bc->bch.nr, card->name, count);
|
|
print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
|
|
}
|
|
}
|
|
|
|
static void
|
|
fill_dma(struct tiger_ch *bc)
|
|
{
|
|
struct tiger_hw *card = bc->bch.hw;
|
|
int count, i, fillempty = 0;
|
|
u32 m, v, n = 0;
|
|
u8 *p;
|
|
|
|
if (bc->free == 0)
|
|
return;
|
|
if (!bc->bch.tx_skb) {
|
|
if (!test_bit(FLG_TX_EMPTY, &bc->bch.Flags))
|
|
return;
|
|
fillempty = 1;
|
|
count = card->send.size >> 1;
|
|
p = bc->bch.fill;
|
|
} else {
|
|
count = bc->bch.tx_skb->len - bc->bch.tx_idx;
|
|
if (count <= 0)
|
|
return;
|
|
pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n",
|
|
card->name, __func__, bc->bch.nr, count, bc->free,
|
|
bc->bch.tx_idx, bc->bch.tx_skb->len, bc->txstate,
|
|
bc->idx, card->send.idx);
|
|
p = bc->bch.tx_skb->data + bc->bch.tx_idx;
|
|
}
|
|
if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
|
|
resync(bc, card);
|
|
if (test_bit(FLG_HDLC, &bc->bch.Flags) && !fillempty) {
|
|
count = isdnhdlc_encode(&bc->hsend, p, count, &i,
|
|
bc->hsbuf, bc->free);
|
|
pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name,
|
|
bc->bch.nr, i, count);
|
|
bc->bch.tx_idx += i;
|
|
bc->free -= count;
|
|
p = bc->hsbuf;
|
|
} else {
|
|
if (count > bc->free)
|
|
count = bc->free;
|
|
if (!fillempty)
|
|
bc->bch.tx_idx += count;
|
|
bc->free -= count;
|
|
}
|
|
m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
|
|
if (fillempty) {
|
|
n = p[0];
|
|
if (!(bc->bch.nr & 1))
|
|
n <<= 8;
|
|
for (i = 0; i < count; i++) {
|
|
if (bc->idx >= card->send.size)
|
|
bc->idx = 0;
|
|
v = card->send.start[bc->idx];
|
|
v &= m;
|
|
v |= n;
|
|
card->send.start[bc->idx++] = v;
|
|
}
|
|
} else {
|
|
for (i = 0; i < count; i++) {
|
|
if (bc->idx >= card->send.size)
|
|
bc->idx = 0;
|
|
v = card->send.start[bc->idx];
|
|
v &= m;
|
|
n = p[i];
|
|
v |= (bc->bch.nr & 1) ? n : n << 8;
|
|
card->send.start[bc->idx++] = v;
|
|
}
|
|
}
|
|
if (debug & DEBUG_HW_BFIFO) {
|
|
snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
|
|
bc->bch.nr, card->name, count);
|
|
print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
|
|
}
|
|
if (bc->free)
|
|
bc_next_frame(bc);
|
|
}
|
|
|
|
|
|
static int
|
|
bc_next_frame(struct tiger_ch *bc)
|
|
{
|
|
int ret = 1;
|
|
|
|
if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len) {
|
|
fill_dma(bc);
|
|
} else {
|
|
dev_kfree_skb(bc->bch.tx_skb);
|
|
if (get_next_bframe(&bc->bch)) {
|
|
fill_dma(bc);
|
|
test_and_clear_bit(FLG_TX_EMPTY, &bc->bch.Flags);
|
|
} else if (test_bit(FLG_TX_EMPTY, &bc->bch.Flags)) {
|
|
fill_dma(bc);
|
|
} else if (test_bit(FLG_FILLEMPTY, &bc->bch.Flags)) {
|
|
test_and_set_bit(FLG_TX_EMPTY, &bc->bch.Flags);
|
|
ret = 0;
|
|
} else {
|
|
ret = 0;
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc)
|
|
{
|
|
int ret;
|
|
|
|
bc->free += card->send.size / 2;
|
|
if (bc->free >= card->send.size) {
|
|
if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) {
|
|
pr_info("%s: B%1d TX underrun state %x\n", card->name,
|
|
bc->bch.nr, bc->txstate);
|
|
bc->txstate |= TX_UNDERRUN;
|
|
}
|
|
bc->free = card->send.size;
|
|
}
|
|
ret = bc_next_frame(bc);
|
|
if (!ret) {
|
|
if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
|
|
fill_hdlc_flag(bc);
|
|
return;
|
|
}
|
|
pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name,
|
|
bc->bch.nr, bc->free, bc->idx, card->send.idx);
|
|
if (!(bc->txstate & (TX_IDLE | TX_INIT))) {
|
|
fill_mem(bc, bc->idx, bc->free, 0xff);
|
|
if (bc->free == card->send.size)
|
|
bc->txstate |= TX_IDLE;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
send_tiger(struct tiger_hw *card, u8 irq_stat)
|
|
{
|
|
int i;
|
|
|
|
/* Note send is via the READ DMA channel */
|
|
if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) {
|
|
pr_info("%s: tiger warn write double dma %x/%x\n",
|
|
card->name, irq_stat, card->last_is0);
|
|
return;
|
|
} else {
|
|
card->last_is0 &= ~NJ_IRQM0_RD_MASK;
|
|
card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK);
|
|
}
|
|
for (i = 0; i < 2; i++) {
|
|
if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags))
|
|
send_tiger_bc(card, &card->bc[i]);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t
|
|
nj_irq(int intno, void *dev_id)
|
|
{
|
|
struct tiger_hw *card = dev_id;
|
|
u8 val, s1val, s0val;
|
|
|
|
spin_lock(&card->lock);
|
|
s0val = inb(card->base | NJ_IRQSTAT0);
|
|
s1val = inb(card->base | NJ_IRQSTAT1);
|
|
if ((s1val & NJ_ISACIRQ) && (s0val == 0)) {
|
|
/* shared IRQ */
|
|
spin_unlock(&card->lock);
|
|
return IRQ_NONE;
|
|
}
|
|
pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val);
|
|
card->irqcnt++;
|
|
if (!(s1val & NJ_ISACIRQ)) {
|
|
val = ReadISAC_nj(card, ISAC_ISTA);
|
|
if (val)
|
|
mISDNisac_irq(&card->isac, val);
|
|
}
|
|
|
|
if (s0val)
|
|
/* write to clear */
|
|
outb(s0val, card->base | NJ_IRQSTAT0);
|
|
else
|
|
goto end;
|
|
s1val = s0val;
|
|
/* set bits in sval to indicate which page is free */
|
|
card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR);
|
|
card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
|
|
if (card->recv.dmacur < card->recv.dmairq)
|
|
s0val = 0x08; /* the 2nd write area is free */
|
|
else
|
|
s0val = 0x04; /* the 1st write area is free */
|
|
|
|
card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
|
|
card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
|
|
if (card->send.dmacur < card->send.dmairq)
|
|
s0val |= 0x02; /* the 2nd read area is free */
|
|
else
|
|
s0val |= 0x01; /* the 1st read area is free */
|
|
|
|
pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name,
|
|
s1val, s0val, card->last_is0,
|
|
card->recv.idx, card->send.idx);
|
|
/* test if we have a DMA interrupt */
|
|
if (s0val != card->last_is0) {
|
|
if ((s0val & NJ_IRQM0_RD_MASK) !=
|
|
(card->last_is0 & NJ_IRQM0_RD_MASK))
|
|
/* got a write dma int */
|
|
send_tiger(card, s0val);
|
|
if ((s0val & NJ_IRQM0_WR_MASK) !=
|
|
(card->last_is0 & NJ_IRQM0_WR_MASK))
|
|
/* got a read dma int */
|
|
recv_tiger(card, s0val);
|
|
}
|
|
end:
|
|
spin_unlock(&card->lock);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int
|
|
nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
|
|
{
|
|
int ret = -EINVAL;
|
|
struct bchannel *bch = container_of(ch, struct bchannel, ch);
|
|
struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
|
|
struct tiger_hw *card = bch->hw;
|
|
struct mISDNhead *hh = mISDN_HEAD_P(skb);
|
|
unsigned long flags;
|
|
|
|
switch (hh->prim) {
|
|
case PH_DATA_REQ:
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
ret = bchannel_senddata(bch, skb);
|
|
if (ret > 0) { /* direct TX */
|
|
fill_dma(bc);
|
|
ret = 0;
|
|
}
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
return ret;
|
|
case PH_ACTIVATE_REQ:
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
|
|
ret = mode_tiger(bc, ch->protocol);
|
|
else
|
|
ret = 0;
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
if (!ret)
|
|
_queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
|
|
NULL, GFP_KERNEL);
|
|
break;
|
|
case PH_DEACTIVATE_REQ:
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
mISDN_clear_bchannel(bch);
|
|
mode_tiger(bc, ISDN_P_NONE);
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
_queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
|
|
NULL, GFP_KERNEL);
|
|
ret = 0;
|
|
break;
|
|
}
|
|
if (!ret)
|
|
dev_kfree_skb(skb);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq)
|
|
{
|
|
return mISDN_ctrl_bchannel(&bc->bch, cq);
|
|
}
|
|
|
|
static int
|
|
nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
|
|
{
|
|
struct bchannel *bch = container_of(ch, struct bchannel, ch);
|
|
struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
|
|
struct tiger_hw *card = bch->hw;
|
|
int ret = -EINVAL;
|
|
u_long flags;
|
|
|
|
pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
|
|
switch (cmd) {
|
|
case CLOSE_CHANNEL:
|
|
test_and_clear_bit(FLG_OPEN, &bch->Flags);
|
|
cancel_work_sync(&bch->workq);
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
mISDN_clear_bchannel(bch);
|
|
mode_tiger(bc, ISDN_P_NONE);
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
ch->protocol = ISDN_P_NONE;
|
|
ch->peer = NULL;
|
|
module_put(THIS_MODULE);
|
|
ret = 0;
|
|
break;
|
|
case CONTROL_CHANNEL:
|
|
ret = channel_bctrl(bc, arg);
|
|
break;
|
|
default:
|
|
pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (cq->op) {
|
|
case MISDN_CTRL_GETOP:
|
|
cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
|
|
break;
|
|
case MISDN_CTRL_LOOP:
|
|
/* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
|
|
if (cq->channel < 0 || cq->channel > 3) {
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel);
|
|
break;
|
|
case MISDN_CTRL_L1_TIMER3:
|
|
ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1);
|
|
break;
|
|
default:
|
|
pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
open_bchannel(struct tiger_hw *card, struct channel_req *rq)
|
|
{
|
|
struct bchannel *bch;
|
|
|
|
if (rq->adr.channel == 0 || rq->adr.channel > 2)
|
|
return -EINVAL;
|
|
if (rq->protocol == ISDN_P_NONE)
|
|
return -EINVAL;
|
|
bch = &card->bc[rq->adr.channel - 1].bch;
|
|
if (test_and_set_bit(FLG_OPEN, &bch->Flags))
|
|
return -EBUSY; /* b-channel can be only open once */
|
|
test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
|
|
bch->ch.protocol = rq->protocol;
|
|
rq->ch = &bch->ch;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* device control function
|
|
*/
|
|
static int
|
|
nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
|
|
{
|
|
struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
|
|
struct dchannel *dch = container_of(dev, struct dchannel, dev);
|
|
struct tiger_hw *card = dch->hw;
|
|
struct channel_req *rq;
|
|
int err = 0;
|
|
|
|
pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
|
|
switch (cmd) {
|
|
case OPEN_CHANNEL:
|
|
rq = arg;
|
|
if (rq->protocol == ISDN_P_TE_S0)
|
|
err = card->isac.open(&card->isac, rq);
|
|
else
|
|
err = open_bchannel(card, rq);
|
|
if (err)
|
|
break;
|
|
if (!try_module_get(THIS_MODULE))
|
|
pr_info("%s: cannot get module\n", card->name);
|
|
break;
|
|
case CLOSE_CHANNEL:
|
|
pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id,
|
|
__builtin_return_address(0));
|
|
module_put(THIS_MODULE);
|
|
break;
|
|
case CONTROL_CHANNEL:
|
|
err = channel_ctrl(card, arg);
|
|
break;
|
|
default:
|
|
pr_debug("%s: %s unknown command %x\n",
|
|
card->name, __func__, cmd);
|
|
return -EINVAL;
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static int
|
|
nj_init_card(struct tiger_hw *card)
|
|
{
|
|
u_long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
nj_disable_hwirq(card);
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
|
|
card->irq = card->pdev->irq;
|
|
if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) {
|
|
pr_info("%s: couldn't get interrupt %d\n",
|
|
card->name, card->irq);
|
|
card->irq = -1;
|
|
return -EIO;
|
|
}
|
|
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
nj_reset(card);
|
|
ret = card->isac.init(&card->isac);
|
|
if (ret)
|
|
goto error;
|
|
ret = inittiger(card);
|
|
if (ret)
|
|
goto error;
|
|
mode_tiger(&card->bc[0], ISDN_P_NONE);
|
|
mode_tiger(&card->bc[1], ISDN_P_NONE);
|
|
error:
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
|
|
static void
|
|
nj_release(struct tiger_hw *card)
|
|
{
|
|
u_long flags;
|
|
int i;
|
|
|
|
if (card->base_s) {
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
nj_disable_hwirq(card);
|
|
mode_tiger(&card->bc[0], ISDN_P_NONE);
|
|
mode_tiger(&card->bc[1], ISDN_P_NONE);
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
card->isac.release(&card->isac);
|
|
release_region(card->base, card->base_s);
|
|
card->base_s = 0;
|
|
}
|
|
if (card->irq > 0)
|
|
free_irq(card->irq, card);
|
|
if (device_is_registered(&card->isac.dch.dev.dev))
|
|
mISDN_unregister_device(&card->isac.dch.dev);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
mISDN_freebchannel(&card->bc[i].bch);
|
|
kfree(card->bc[i].hsbuf);
|
|
kfree(card->bc[i].hrbuf);
|
|
}
|
|
if (card->dma_p)
|
|
dma_free_coherent(&card->pdev->dev, NJ_DMA_SIZE, card->dma_p,
|
|
card->dma);
|
|
write_lock_irqsave(&card_lock, flags);
|
|
list_del(&card->list);
|
|
write_unlock_irqrestore(&card_lock, flags);
|
|
pci_clear_master(card->pdev);
|
|
pci_disable_device(card->pdev);
|
|
pci_set_drvdata(card->pdev, NULL);
|
|
kfree(card);
|
|
}
|
|
|
|
|
|
static int
|
|
nj_setup(struct tiger_hw *card)
|
|
{
|
|
card->base = pci_resource_start(card->pdev, 0);
|
|
card->base_s = pci_resource_len(card->pdev, 0);
|
|
if (!request_region(card->base, card->base_s, card->name)) {
|
|
pr_info("%s: NETjet config port %#x-%#x already in use\n",
|
|
card->name, card->base,
|
|
(u32)(card->base + card->base_s - 1));
|
|
card->base_s = 0;
|
|
return -EIO;
|
|
}
|
|
ASSIGN_FUNC(nj, ISAC, card->isac);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int
|
|
setup_instance(struct tiger_hw *card)
|
|
{
|
|
int i, err;
|
|
u_long flags;
|
|
|
|
snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1);
|
|
write_lock_irqsave(&card_lock, flags);
|
|
list_add_tail(&card->list, &Cards);
|
|
write_unlock_irqrestore(&card_lock, flags);
|
|
|
|
_set_debug(card);
|
|
card->isac.name = card->name;
|
|
spin_lock_init(&card->lock);
|
|
card->isac.hwlock = &card->lock;
|
|
mISDNisac_init(&card->isac, card);
|
|
|
|
card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
|
|
(1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
|
|
card->isac.dch.dev.D.ctrl = nj_dctrl;
|
|
for (i = 0; i < 2; i++) {
|
|
card->bc[i].bch.nr = i + 1;
|
|
set_channelmap(i + 1, card->isac.dch.dev.channelmap);
|
|
mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM,
|
|
NJ_DMA_RXSIZE >> 1);
|
|
card->bc[i].bch.hw = card;
|
|
card->bc[i].bch.ch.send = nj_l2l1B;
|
|
card->bc[i].bch.ch.ctrl = nj_bctrl;
|
|
card->bc[i].bch.ch.nr = i + 1;
|
|
list_add(&card->bc[i].bch.ch.list,
|
|
&card->isac.dch.dev.bchannels);
|
|
card->bc[i].bch.hw = card;
|
|
}
|
|
err = nj_setup(card);
|
|
if (err)
|
|
goto error;
|
|
err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
|
|
card->name);
|
|
if (err)
|
|
goto error;
|
|
err = nj_init_card(card);
|
|
if (!err) {
|
|
nj_cnt++;
|
|
pr_notice("Netjet %d cards installed\n", nj_cnt);
|
|
return 0;
|
|
}
|
|
error:
|
|
nj_release(card);
|
|
return err;
|
|
}
|
|
|
|
static int
|
|
nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
int err = -ENOMEM;
|
|
int cfg;
|
|
struct tiger_hw *card;
|
|
|
|
if (pdev->subsystem_vendor == 0x8086 &&
|
|
pdev->subsystem_device == 0x0003) {
|
|
pr_notice("Netjet: Digium X100P/X101P not handled\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (pdev->subsystem_vendor == 0x55 &&
|
|
pdev->subsystem_device == 0x02) {
|
|
pr_notice("Netjet: Enter!Now not handled yet\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (pdev->subsystem_vendor == 0xb100 &&
|
|
pdev->subsystem_device == 0x0003) {
|
|
pr_notice("Netjet: Digium TDM400P not handled yet\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
card = kzalloc(sizeof(struct tiger_hw), GFP_KERNEL);
|
|
if (!card) {
|
|
pr_info("No kmem for Netjet\n");
|
|
return err;
|
|
}
|
|
|
|
card->pdev = pdev;
|
|
|
|
err = pci_enable_device(pdev);
|
|
if (err) {
|
|
kfree(card);
|
|
return err;
|
|
}
|
|
|
|
printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n",
|
|
pci_name(pdev));
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* the TJ300 and TJ320 must be detected, the IRQ handling is different
|
|
* unfortunately the chips use the same device ID, but the TJ320 has
|
|
* the bit20 in status PCI cfg register set
|
|
*/
|
|
pci_read_config_dword(pdev, 0x04, &cfg);
|
|
if (cfg & 0x00100000)
|
|
card->typ = NETJET_S_TJ320;
|
|
else
|
|
card->typ = NETJET_S_TJ300;
|
|
|
|
card->base = pci_resource_start(pdev, 0);
|
|
pci_set_drvdata(pdev, card);
|
|
err = setup_instance(card);
|
|
if (err)
|
|
pci_set_drvdata(pdev, NULL);
|
|
|
|
return err;
|
|
}
|
|
|
|
|
|
static void nj_remove(struct pci_dev *pdev)
|
|
{
|
|
struct tiger_hw *card = pci_get_drvdata(pdev);
|
|
|
|
if (card)
|
|
nj_release(card);
|
|
else
|
|
pr_info("%s drvdata already removed\n", __func__);
|
|
}
|
|
|
|
/* We cannot select cards with PCI_SUB... IDs, since here are cards with
|
|
* SUB IDs set to PCI_ANY_ID, so we need to match all and reject
|
|
* known other cards which not work with this driver - see probe function */
|
|
static const struct pci_device_id nj_pci_ids[] = {
|
|
{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300,
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, nj_pci_ids);
|
|
|
|
static struct pci_driver nj_driver = {
|
|
.name = "netjet",
|
|
.probe = nj_probe,
|
|
.remove = nj_remove,
|
|
.id_table = nj_pci_ids,
|
|
};
|
|
|
|
static int __init nj_init(void)
|
|
{
|
|
int err;
|
|
|
|
pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV);
|
|
err = pci_register_driver(&nj_driver);
|
|
return err;
|
|
}
|
|
|
|
static void __exit nj_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&nj_driver);
|
|
}
|
|
|
|
module_init(nj_init);
|
|
module_exit(nj_cleanup);
|