578 lines
17 KiB
C
578 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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/* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */
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#define USE_CLSR BIT(0)
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#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
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#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
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#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
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#define SPINOR_REG_CYPRESS_CFR1V 0x00800002
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#define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */
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#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
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#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
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#define SPINOR_REG_CYPRESS_CFR3V 0x00800004
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#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */
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#define SPINOR_REG_CYPRESS_CFR5V 0x00800006
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#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
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#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
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#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
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#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \
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(SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
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SPINOR_REG_CYPRESS_CFR5_OPI)
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#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6
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#define SPINOR_OP_CYPRESS_RD_FAST 0xee
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/* Cypress SPI NOR flash operations. */
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#define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \
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SPI_MEM_OP_ADDR(naddr, addr, 0), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
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#define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \
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SPI_MEM_OP_ADDR(naddr, addr, 0), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_IN(1, buf, 0))
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#define SPANSION_CLSR_OP \
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
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/* Use 24 dummy cycles for memory array reads. */
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*buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
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SPINOR_REG_CYPRESS_CFR2V, 1, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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nor->read_dummy = 24;
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/* Set the octal and DTR enable bits. */
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buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
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SPINOR_REG_CYPRESS_CFR5V, 1, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf,
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SNOR_PROTO_8_8_8_DTR);
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if (ret) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
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return ret;
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}
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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return 0;
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}
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static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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/*
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* The register is 1-byte wide, but 1-byte transactions are not allowed
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* in 8D-8D-8D mode. Since there is no register at the next location,
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* just initialize the value to 0 and let the transaction go on.
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*/
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buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS;
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buf[1] = 0;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes,
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SPINOR_REG_CYPRESS_CFR5V, 2, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
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if (ret) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
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return ret;
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}
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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return 0;
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}
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/**
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* cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
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* register.
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* @nor: pointer to a 'struct spi_nor'
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*
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* It is recommended to update volatile registers in the field application due
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* to a risk of the non-volatile registers corruption by power interrupt. This
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* function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
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* bit in the CFR1 non-volatile in advance (typically by a Flash programmer
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* before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
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* also set during Flash power-up.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
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u8 cfr1v_written;
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int ret;
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op = (struct spi_mem_op)
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CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
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SPINOR_REG_CYPRESS_CFR1V,
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nor->bouncebuf);
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ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN)
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return 0;
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/* Update the Quad Enable bit. */
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nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
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SPINOR_REG_CYPRESS_CFR1V, 1,
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nor->bouncebuf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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cfr1v_written = nor->bouncebuf[0];
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/* Read back and check it. */
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op = (struct spi_mem_op)
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CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
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SPINOR_REG_CYPRESS_CFR1V,
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nor->bouncebuf);
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ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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if (nor->bouncebuf[0] != cfr1v_written) {
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dev_err(nor->dev, "CFR1: Read back test failed\n");
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return -EIO;
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}
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return 0;
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}
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/**
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* cypress_nor_set_page_size() - Set page size which corresponds to the flash
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* configuration.
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* @nor: pointer to a 'struct spi_nor'
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*
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* The BFPT table advertises a 512B or 256B page size depending on part but the
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* page size is actually configurable (with the default being 256B). Read from
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* CFR3V[4] and set the correct size.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int cypress_nor_set_page_size(struct spi_nor *nor)
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{
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struct spi_mem_op op =
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CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
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SPINOR_REG_CYPRESS_CFR3V,
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nor->bouncebuf);
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int ret;
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ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)
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nor->params->page_size = 512;
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else
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nor->params->page_size = 256;
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return 0;
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}
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static void cypress_nor_ecc_init(struct spi_nor *nor)
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{
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/*
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* Programming is supported only in 16-byte ECC data unit granularity.
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* Byte-programming, bit-walking, or multiple program operations to the
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* same ECC data unit without an erase are not allowed.
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*/
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nor->params->writesize = 16;
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nor->flags |= SNOR_F_ECC;
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}
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static int
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s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/* Replace Quad Enable with volatile version */
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nor->params->quad_enable = cypress_nor_quad_enable_volatile;
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return cypress_nor_set_page_size(nor);
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}
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static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
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{
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struct spi_nor_erase_type *erase_type =
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nor->params->erase_map.erase_type;
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unsigned int i;
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/*
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* In some parts, 3byte erase opcodes are advertised by 4BAIT.
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* Convert them to 4byte erase opcodes.
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*/
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for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
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switch (erase_type[i].opcode) {
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case SPINOR_OP_SE:
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erase_type[i].opcode = SPINOR_OP_SE_4B;
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break;
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case SPINOR_OP_BE_4K:
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erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
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break;
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default:
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break;
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}
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}
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}
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static void s25hx_t_late_init(struct spi_nor *nor)
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{
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/* Fast Read 4B requires mode cycles */
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nor->params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
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cypress_nor_ecc_init(nor);
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}
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static struct spi_nor_fixups s25hx_t_fixups = {
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.post_bfpt = s25hx_t_post_bfpt_fixup,
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.post_sfdp = s25hx_t_post_sfdp_fixup,
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.late_init = s25hx_t_late_init,
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};
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/**
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* cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
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* @nor: pointer to a 'struct spi_nor'
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* @enable: whether to enable or disable Octal DTR
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*
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* This also sets the memory access latency cycles to 24 to allow the flash to
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* run at up to 200MHz.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
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{
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return enable ? cypress_nor_octal_dtr_en(nor) :
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cypress_nor_octal_dtr_dis(nor);
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}
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static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
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{
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/*
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* On older versions of the flash the xSPI Profile 1.0 table has the
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* 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
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*/
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if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
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nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
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SPINOR_OP_CYPRESS_RD_FAST;
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/* This flash is also missing the 4-byte Page Program opcode bit. */
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spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
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SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
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/*
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* Since xSPI Page Program opcode is backward compatible with
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* Legacy SPI, use Legacy SPI opcode there as well.
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*/
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spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
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SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
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/*
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* The xSPI Profile 1.0 table advertises the number of additional
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* address bytes needed for Read Status Register command as 0 but the
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* actual value for that is 4.
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*/
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nor->params->rdsr_addr_nbytes = 4;
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}
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static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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return cypress_nor_set_page_size(nor);
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}
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static void s28hx_t_late_init(struct spi_nor *nor)
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{
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nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable;
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cypress_nor_ecc_init(nor);
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}
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static const struct spi_nor_fixups s28hx_t_fixups = {
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.post_sfdp = s28hx_t_post_sfdp_fixup,
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.post_bfpt = s28hx_t_post_bfpt_fixup,
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.late_init = s28hx_t_late_init,
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};
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static int
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s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* The S25FS-S chip family reports 512-byte pages in BFPT but
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* in reality the write buffer still wraps at the safe default
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* of 256 bytes. Overwrite the page size advertised by BFPT
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* to get the writes working.
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*/
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nor->params->page_size = 256;
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return 0;
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}
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static const struct spi_nor_fixups s25fs_s_nor_fixups = {
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.post_bfpt = s25fs_s_nor_post_bfpt_fixups,
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};
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static const struct flash_info spansion_nor_parts[] = {
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/* Spansion/Cypress -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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*/
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
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NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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.fixups = &s25fs_s_nor_fixups, },
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{ "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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.fixups = &s25fs_s_nor_fixups, },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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MFR_FLAGS(USE_CLSR)
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},
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) },
|
|
{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) },
|
|
{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
|
|
SPI_NOR_QUAD_READ) },
|
|
{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
|
|
SPI_NOR_QUAD_READ) },
|
|
{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
|
|
SPI_NOR_QUAD_READ) },
|
|
{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
|
|
SPI_NOR_QUAD_READ) },
|
|
{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
|
|
SPI_NOR_QUAD_READ) },
|
|
{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64)
|
|
NO_SFDP_FLAGS(SECT_4K) },
|
|
{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128)
|
|
NO_SFDP_FLAGS(SECT_4K) },
|
|
{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
|
|
{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
|
|
{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
|
|
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
|
|
{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
|
|
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
|
|
{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
|
|
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
|
|
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
|
|
{ "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
|
|
PARSE_SFDP
|
|
MFR_FLAGS(USE_CLSR)
|
|
.fixups = &s25hx_t_fixups },
|
|
{ "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512)
|
|
PARSE_SFDP
|
|
MFR_FLAGS(USE_CLSR)
|
|
.fixups = &s25hx_t_fixups },
|
|
{ "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256)
|
|
PARSE_SFDP
|
|
MFR_FLAGS(USE_CLSR)
|
|
.fixups = &s25hx_t_fixups },
|
|
{ "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512)
|
|
PARSE_SFDP
|
|
MFR_FLAGS(USE_CLSR)
|
|
.fixups = &s25hx_t_fixups },
|
|
{ "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
|
|
FLAGS(SPI_NOR_NO_ERASE) },
|
|
{ "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256)
|
|
PARSE_SFDP
|
|
.fixups = &s28hx_t_fixups,
|
|
},
|
|
{ "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512)
|
|
PARSE_SFDP
|
|
.fixups = &s28hx_t_fixups,
|
|
},
|
|
{ "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256)
|
|
PARSE_SFDP
|
|
.fixups = &s28hx_t_fixups,
|
|
},
|
|
{ "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512)
|
|
PARSE_SFDP
|
|
.fixups = &s28hx_t_fixups,
|
|
},
|
|
};
|
|
|
|
/**
|
|
* spansion_nor_clear_sr() - Clear the Status Register.
|
|
* @nor: pointer to 'struct spi_nor'.
|
|
*/
|
|
static void spansion_nor_clear_sr(struct spi_nor *nor)
|
|
{
|
|
int ret;
|
|
|
|
if (nor->spimem) {
|
|
struct spi_mem_op op = SPANSION_CLSR_OP;
|
|
|
|
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
|
|
|
|
ret = spi_mem_exec_op(nor->spimem, &op);
|
|
} else {
|
|
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
|
|
NULL, 0);
|
|
}
|
|
|
|
if (ret)
|
|
dev_dbg(nor->dev, "error %d clearing SR\n", ret);
|
|
}
|
|
|
|
/**
|
|
* spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
|
|
* flash is ready for new commands and clear it if there are any errors.
|
|
* @nor: pointer to 'struct spi_nor'.
|
|
*
|
|
* Return: 1 if ready, 0 if not ready, -errno on errors.
|
|
*/
|
|
static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
|
|
{
|
|
int ret;
|
|
|
|
ret = spi_nor_read_sr(nor, nor->bouncebuf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
|
|
if (nor->bouncebuf[0] & SR_E_ERR)
|
|
dev_err(nor->dev, "Erase Error occurred\n");
|
|
else
|
|
dev_err(nor->dev, "Programming Error occurred\n");
|
|
|
|
spansion_nor_clear_sr(nor);
|
|
|
|
/*
|
|
* WEL bit remains set to one when an erase or page program
|
|
* error occurs. Issue a Write Disable command to protect
|
|
* against inadvertent writes that can possibly corrupt the
|
|
* contents of the memory.
|
|
*/
|
|
ret = spi_nor_write_disable(nor);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return -EIO;
|
|
}
|
|
|
|
return !(nor->bouncebuf[0] & SR_WIP);
|
|
}
|
|
|
|
static void spansion_nor_late_init(struct spi_nor *nor)
|
|
{
|
|
if (nor->params->size > SZ_16M) {
|
|
nor->flags |= SNOR_F_4B_OPCODES;
|
|
/* No small sector erase for 4-byte command set */
|
|
nor->erase_opcode = SPINOR_OP_SE;
|
|
nor->mtd.erasesize = nor->info->sector_size;
|
|
}
|
|
|
|
if (nor->info->mfr_flags & USE_CLSR)
|
|
nor->params->ready = spansion_nor_sr_ready_and_clear;
|
|
}
|
|
|
|
static const struct spi_nor_fixups spansion_nor_fixups = {
|
|
.late_init = spansion_nor_late_init,
|
|
};
|
|
|
|
const struct spi_nor_manufacturer spi_nor_spansion = {
|
|
.name = "spansion",
|
|
.parts = spansion_nor_parts,
|
|
.nparts = ARRAY_SIZE(spansion_nor_parts),
|
|
.fixups = &spansion_nor_fixups,
|
|
};
|