423 lines
12 KiB
C
423 lines
12 KiB
C
/*
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* Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "common.h"
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#include "regs.h"
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enum {
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IDT75P52100 = 4,
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IDT75N43102 = 5
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};
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/* DBGI command mode */
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enum {
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DBGI_MODE_MBUS = 0,
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DBGI_MODE_IDT52100 = 5
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};
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/* IDT 75P52100 commands */
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#define IDT_CMD_READ 0
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#define IDT_CMD_WRITE 1
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#define IDT_CMD_SEARCH 2
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#define IDT_CMD_LEARN 3
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/* IDT LAR register address and value for 144-bit mode (low 32 bits) */
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#define IDT_LAR_ADR0 0x180006
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#define IDT_LAR_MODE144 0xffff0000
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/* IDT SCR and SSR addresses (low 32 bits) */
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#define IDT_SCR_ADR0 0x180000
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#define IDT_SSR0_ADR0 0x180002
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#define IDT_SSR1_ADR0 0x180004
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/* IDT GMR base address (low 32 bits) */
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#define IDT_GMR_BASE_ADR0 0x180020
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/* IDT data and mask array base addresses (low 32 bits) */
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#define IDT_DATARY_BASE_ADR0 0
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#define IDT_MSKARY_BASE_ADR0 0x80000
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/* IDT 75N43102 commands */
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#define IDT4_CMD_SEARCH144 3
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#define IDT4_CMD_WRITE 4
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#define IDT4_CMD_READ 5
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/* IDT 75N43102 SCR address (low 32 bits) */
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#define IDT4_SCR_ADR0 0x3
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/* IDT 75N43102 GMR base addresses (low 32 bits) */
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#define IDT4_GMR_BASE0 0x10
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#define IDT4_GMR_BASE1 0x20
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#define IDT4_GMR_BASE2 0x30
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/* IDT 75N43102 data and mask array base addresses (low 32 bits) */
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#define IDT4_DATARY_BASE_ADR0 0x1000000
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#define IDT4_MSKARY_BASE_ADR0 0x2000000
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#define MAX_WRITE_ATTEMPTS 5
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#define MAX_ROUTES 2048
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/*
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* Issue a command to the TCAM and wait for its completion. The address and
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* any data required by the command must have been setup by the caller.
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*/
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static int mc5_cmd_write(struct adapter *adapter, u32 cmd)
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{
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t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd);
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return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS,
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F_DBGIRSPVALID, 1, MAX_WRITE_ATTEMPTS, 1);
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}
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static inline void dbgi_wr_data3(struct adapter *adapter, u32 v1, u32 v2,
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u32 v3)
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{
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t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1);
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t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2);
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t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3);
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}
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/*
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* Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
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* command cmd. The data to be written must have been set up by the caller.
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* Returns -1 on failure, 0 on success.
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*/
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static int mc5_write(struct adapter *adapter, u32 addr_lo, u32 cmd)
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{
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t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo);
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if (mc5_cmd_write(adapter, cmd) == 0)
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return 0;
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CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n",
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addr_lo);
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return -1;
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}
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static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base,
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u32 data_array_base, u32 write_cmd,
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int addr_shift)
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{
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unsigned int i;
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struct adapter *adap = mc5->adapter;
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/*
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* We need the size of the TCAM data and mask arrays in terms of
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* 72-bit entries.
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*/
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unsigned int size72 = mc5->tcam_size;
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unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
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if (mc5->mode == MC5_MODE_144_BIT) {
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size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */
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server_base *= 2;
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}
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/* Clear the data array */
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dbgi_wr_data3(adap, 0, 0, 0);
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for (i = 0; i < size72; i++)
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if (mc5_write(adap, data_array_base + (i << addr_shift),
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write_cmd))
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return -1;
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/* Initialize the mask array. */
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dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
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for (i = 0; i < size72; i++) {
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if (i == server_base) /* entering server or routing region */
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t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0,
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mc5->mode == MC5_MODE_144_BIT ?
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0xfffffff9 : 0xfffffffd);
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if (mc5_write(adap, mask_array_base + (i << addr_shift),
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write_cmd))
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return -1;
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}
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return 0;
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}
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static int init_idt52100(struct mc5 *mc5)
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{
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int i;
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struct adapter *adap = mc5->adapter;
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t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
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V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15));
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t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2);
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/*
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* Use GMRs 14-15 for ELOOKUP, GMRs 12-13 for SYN lookups, and
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* GMRs 8-9 for ACK- and AOPEN searches.
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*/
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t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE);
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t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE);
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t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH);
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t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN);
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t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);
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t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN);
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t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH);
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t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN);
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t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH);
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t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);
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t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE);
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t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ);
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/* Set DBGI command mode for IDT TCAM. */
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t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
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/* Set up LAR */
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dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);
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if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE))
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goto err;
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/* Set up SSRs */
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dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
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if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) ||
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mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE))
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goto err;
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/* Set up GMRs */
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for (i = 0; i < 32; ++i) {
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if (i >= 12 && i < 15)
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dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
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else if (i == 15)
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dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
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else
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dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
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if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE))
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goto err;
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}
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/* Set up SCR */
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dbgi_wr_data3(adap, 1, 0, 0);
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if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE))
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goto err;
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return init_mask_data_array(mc5, IDT_MSKARY_BASE_ADR0,
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IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0);
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err:
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return -EIO;
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}
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static int init_idt43102(struct mc5 *mc5)
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{
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int i;
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struct adapter *adap = mc5->adapter;
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t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
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adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :
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V_RDLAT(0xd) | V_SRCHLAT(0x12));
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/*
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* Use GMRs 24-25 for ELOOKUP, GMRs 20-21 for SYN lookups, and no mask
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* for ACK- and AOPEN searches.
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*/
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t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE);
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t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE);
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t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD,
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IDT4_CMD_SEARCH144 | 0x3800);
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t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144);
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t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);
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t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);
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t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);
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t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE);
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t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ);
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t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3);
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/* Set DBGI command mode for IDT TCAM. */
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t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
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/* Set up GMRs */
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dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
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for (i = 0; i < 7; ++i)
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if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE))
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goto err;
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for (i = 0; i < 4; ++i)
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if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE))
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goto err;
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dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
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if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) ||
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mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) ||
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mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE))
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goto err;
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dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
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if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE))
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goto err;
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/* Set up SCR */
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dbgi_wr_data3(adap, 0xf0000000, 0, 0);
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if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE))
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goto err;
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return init_mask_data_array(mc5, IDT4_MSKARY_BASE_ADR0,
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IDT4_DATARY_BASE_ADR0, IDT4_CMD_WRITE, 1);
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err:
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return -EIO;
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}
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/* Put MC5 in DBGI mode. */
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static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5)
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{
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t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
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V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_DBGIEN);
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}
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/* Put MC5 in M-Bus mode. */
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static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
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{
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t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
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V_TMMODE(mc5->mode == MC5_MODE_72_BIT) |
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V_COMPEN(mc5->mode == MC5_MODE_72_BIT) |
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V_PRTYEN(mc5->parity_enabled) | F_MBUSEN);
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}
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/*
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* Initialization that requires the OS and protocol layers to already
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* be initialized goes here.
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*/
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int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
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unsigned int nroutes)
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{
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u32 cfg;
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int err;
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unsigned int tcam_size = mc5->tcam_size;
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struct adapter *adap = mc5->adapter;
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if (!tcam_size)
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return 0;
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if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size)
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return -EINVAL;
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/* Reset the TCAM */
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cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
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cfg |= V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_TMRST;
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t3_write_reg(adap, A_MC5_DB_CONFIG, cfg);
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if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
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CH_ERR(adap, "TCAM reset timed out\n");
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return -1;
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}
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t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes);
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t3_write_reg(adap, A_MC5_DB_FILTER_TABLE,
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tcam_size - nroutes - nfilters);
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t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
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tcam_size - nroutes - nfilters - nservers);
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mc5->parity_enabled = 1;
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/* All the TCAM addresses we access have only the low 32 bits non 0 */
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t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
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t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
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mc5_dbgi_mode_enable(mc5);
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switch (mc5->part_type) {
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case IDT75P52100:
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err = init_idt52100(mc5);
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break;
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case IDT75N43102:
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err = init_idt43102(mc5);
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break;
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default:
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CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type);
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err = -EINVAL;
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break;
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}
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mc5_dbgi_mode_disable(mc5);
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return err;
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}
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#define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR)
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/*
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* MC5 interrupt handler
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*/
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void t3_mc5_intr_handler(struct mc5 *mc5)
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{
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struct adapter *adap = mc5->adapter;
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u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
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if ((cause & F_PARITYERR) && mc5->parity_enabled) {
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CH_ALERT(adap, "MC5 parity error\n");
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mc5->stats.parity_err++;
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}
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if (cause & F_REQQPARERR) {
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CH_ALERT(adap, "MC5 request queue parity error\n");
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mc5->stats.reqq_parity_err++;
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}
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if (cause & F_DISPQPARERR) {
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CH_ALERT(adap, "MC5 dispatch queue parity error\n");
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mc5->stats.dispq_parity_err++;
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}
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if (cause & F_ACTRGNFULL)
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mc5->stats.active_rgn_full++;
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if (cause & F_NFASRCHFAIL)
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mc5->stats.nfa_srch_err++;
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if (cause & F_UNKNOWNCMD)
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mc5->stats.unknown_cmd++;
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if (cause & F_DELACTEMPTY)
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mc5->stats.del_act_empty++;
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if (cause & MC5_INT_FATAL)
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t3_fatal_err(adap);
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t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause);
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}
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void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode)
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{
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#define K * 1024
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static unsigned int tcam_part_size[] = { /* in K 72-bit entries */
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64 K, 128 K, 256 K, 32 K
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};
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#undef K
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u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
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mc5->adapter = adapter;
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mc5->mode = (unsigned char)mode;
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mc5->part_type = (unsigned char)G_TMTYPE(cfg);
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if (cfg & F_TMTYPEHI)
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mc5->part_type |= 4;
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mc5->tcam_size = tcam_part_size[G_TMPARTSIZE(cfg)];
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if (mode == MC5_MODE_144_BIT)
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mc5->tcam_size /= 2;
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}
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