140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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* Google virtual Ethernet (gve) driver
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*
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* Copyright (C) 2015-2019 Google, Inc.
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*/
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/* GVE Transmit Descriptor formats */
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#ifndef _GVE_DESC_H_
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#define _GVE_DESC_H_
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#include <linux/build_bug.h>
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/* A note on seg_addrs
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*
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* Base addresses encoded in seg_addr are not assumed to be physical
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* addresses. The ring format assumes these come from some linear address
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* space. This could be physical memory, kernel virtual memory, user virtual
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* memory.
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* If raw dma addressing is not supported then gVNIC uses lists of registered
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* pages. Each queue is assumed to be associated with a single such linear
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* address space to ensure a consistent meaning for seg_addrs posted to its
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* rings.
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*/
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struct gve_tx_pkt_desc {
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u8 type_flags; /* desc type is lower 4 bits, flags upper */
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u8 l4_csum_offset; /* relative offset of L4 csum word */
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u8 l4_hdr_offset; /* Offset of start of L4 headers in packet */
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u8 desc_cnt; /* Total descriptors for this packet */
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__be16 len; /* Total length of this packet (in bytes) */
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__be16 seg_len; /* Length of this descriptor's segment */
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__be64 seg_addr; /* Base address (see note) of this segment */
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} __packed;
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struct gve_tx_mtd_desc {
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u8 type_flags; /* type is lower 4 bits, subtype upper */
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u8 path_state; /* state is lower 4 bits, hash type upper */
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__be16 reserved0;
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__be32 path_hash;
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__be64 reserved1;
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} __packed;
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struct gve_tx_seg_desc {
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u8 type_flags; /* type is lower 4 bits, flags upper */
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u8 l3_offset; /* TSO: 2 byte units to start of IPH */
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__be16 reserved;
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__be16 mss; /* TSO MSS */
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__be16 seg_len;
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__be64 seg_addr;
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} __packed;
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/* GVE Transmit Descriptor Types */
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#define GVE_TXD_STD (0x0 << 4) /* Std with Host Address */
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#define GVE_TXD_TSO (0x1 << 4) /* TSO with Host Address */
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#define GVE_TXD_SEG (0x2 << 4) /* Seg with Host Address */
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#define GVE_TXD_MTD (0x3 << 4) /* Metadata */
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/* GVE Transmit Descriptor Flags for Std Pkts */
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#define GVE_TXF_L4CSUM BIT(0) /* Need csum offload */
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#define GVE_TXF_TSTAMP BIT(2) /* Timestamp required */
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/* GVE Transmit Descriptor Flags for TSO Segs */
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#define GVE_TXSF_IPV6 BIT(1) /* IPv6 TSO */
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/* GVE Transmit Descriptor Options for MTD Segs */
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#define GVE_MTD_SUBTYPE_PATH 0
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#define GVE_MTD_PATH_STATE_DEFAULT 0
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#define GVE_MTD_PATH_STATE_TIMEOUT 1
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#define GVE_MTD_PATH_STATE_CONGESTION 2
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#define GVE_MTD_PATH_STATE_RETRANSMIT 3
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#define GVE_MTD_PATH_HASH_NONE (0x0 << 4)
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#define GVE_MTD_PATH_HASH_L4 (0x1 << 4)
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/* GVE Receive Packet Descriptor */
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/* The start of an ethernet packet comes 2 bytes into the rx buffer.
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* gVNIC adds this padding so that both the DMA and the L3/4 protocol header
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* access is aligned.
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*/
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#define GVE_RX_PAD 2
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struct gve_rx_desc {
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u8 padding[48];
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__be32 rss_hash; /* Receive-side scaling hash (Toeplitz for gVNIC) */
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__be16 mss;
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__be16 reserved; /* Reserved to zero */
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u8 hdr_len; /* Header length (L2-L4) including padding */
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u8 hdr_off; /* 64-byte-scaled offset into RX_DATA entry */
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__sum16 csum; /* 1's-complement partial checksum of L3+ bytes */
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__be16 len; /* Length of the received packet */
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__be16 flags_seq; /* Flags [15:3] and sequence number [2:0] (1-7) */
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} __packed;
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static_assert(sizeof(struct gve_rx_desc) == 64);
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/* If the device supports raw dma addressing then the addr in data slot is
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* the dma address of the buffer.
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* If the device only supports registered segments then the addr is a byte
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* offset into the registered segment (an ordered list of pages) where the
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* buffer is.
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*/
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union gve_rx_data_slot {
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__be64 qpl_offset;
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__be64 addr;
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};
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/* GVE Recive Packet Descriptor Seq No */
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#define GVE_SEQNO(x) (be16_to_cpu(x) & 0x7)
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/* GVE Recive Packet Descriptor Flags */
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#define GVE_RXFLG(x) cpu_to_be16(1 << (3 + (x)))
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#define GVE_RXF_FRAG GVE_RXFLG(3) /* IP Fragment */
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#define GVE_RXF_IPV4 GVE_RXFLG(4) /* IPv4 */
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#define GVE_RXF_IPV6 GVE_RXFLG(5) /* IPv6 */
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#define GVE_RXF_TCP GVE_RXFLG(6) /* TCP Packet */
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#define GVE_RXF_UDP GVE_RXFLG(7) /* UDP Packet */
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#define GVE_RXF_ERR GVE_RXFLG(8) /* Packet Error Detected */
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#define GVE_RXF_PKT_CONT GVE_RXFLG(10) /* Multi Fragment RX packet */
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/* GVE IRQ */
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#define GVE_IRQ_ACK BIT(31)
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#define GVE_IRQ_MASK BIT(30)
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#define GVE_IRQ_EVENT BIT(29)
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static inline bool gve_needs_rss(__be16 flag)
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{
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if (flag & GVE_RXF_FRAG)
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return false;
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if (flag & (GVE_RXF_IPV4 | GVE_RXF_IPV6))
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return true;
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return false;
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}
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static inline u8 gve_next_seqno(u8 seq)
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{
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return (seq + 1) == 8 ? 1 : seq + 1;
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}
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#endif /* _GVE_DESC_H_ */
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