204 lines
6.9 KiB
C
204 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef HINIC_HW_API_CMD_H
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#define HINIC_HW_API_CMD_H
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#include <linux/types.h>
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#include <linux/semaphore.h>
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#include "hinic_hw_if.h"
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#define HINIC_API_CMD_PI_IDX_SHIFT 0
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#define HINIC_API_CMD_PI_IDX_MASK 0xFFFFFF
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#define HINIC_API_CMD_PI_SET(val, member) \
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(((u32)(val) & HINIC_API_CMD_PI_##member##_MASK) << \
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HINIC_API_CMD_PI_##member##_SHIFT)
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#define HINIC_API_CMD_PI_CLEAR(val, member) \
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((val) & (~(HINIC_API_CMD_PI_##member##_MASK \
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<< HINIC_API_CMD_PI_##member##_SHIFT)))
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#define HINIC_API_CMD_CHAIN_REQ_RESTART_SHIFT 1
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#define HINIC_API_CMD_CHAIN_REQ_RESTART_MASK 0x1
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#define HINIC_API_CMD_CHAIN_REQ_SET(val, member) \
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(((u32)(val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \
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HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)
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#define HINIC_API_CMD_CHAIN_REQ_GET(val, member) \
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(((val) >> HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT) & \
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HINIC_API_CMD_CHAIN_REQ_##member##_MASK)
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#define HINIC_API_CMD_CHAIN_REQ_CLEAR(val, member) \
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((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK \
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<< HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)))
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#define HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_SHIFT 1
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#define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_SHIFT 2
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#define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_SHIFT 4
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#define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_SHIFT 8
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#define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_SHIFT 28
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#define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_SHIFT 30
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#define HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_MASK 0x1
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#define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_MASK 0x1
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#define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_MASK 0x1
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#define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_MASK 0x3
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#define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_MASK 0x3
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#define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_MASK 0x3
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#define HINIC_API_CMD_CHAIN_CTRL_SET(val, member) \
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(((u32)(val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \
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HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)
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#define HINIC_API_CMD_CHAIN_CTRL_CLEAR(val, member) \
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((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK \
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<< HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)))
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#define HINIC_API_CMD_CELL_CTRL_DATA_SZ_SHIFT 0
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#define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_SHIFT 16
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#define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_SHIFT 24
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#define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_SHIFT 56
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#define HINIC_API_CMD_CELL_CTRL_DATA_SZ_MASK 0x3F
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#define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_MASK 0x3F
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#define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_MASK 0x3F
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#define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_MASK 0xFF
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#define HINIC_API_CMD_CELL_CTRL_SET(val, member) \
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((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \
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HINIC_API_CMD_CELL_CTRL_##member##_SHIFT)
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#define HINIC_API_CMD_DESC_API_TYPE_SHIFT 0
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#define HINIC_API_CMD_DESC_RD_WR_SHIFT 1
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#define HINIC_API_CMD_DESC_MGMT_BYPASS_SHIFT 2
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#define HINIC_API_CMD_DESC_DEST_SHIFT 32
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#define HINIC_API_CMD_DESC_SIZE_SHIFT 40
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#define HINIC_API_CMD_DESC_XOR_CHKSUM_SHIFT 56
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#define HINIC_API_CMD_DESC_API_TYPE_MASK 0x1
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#define HINIC_API_CMD_DESC_RD_WR_MASK 0x1
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#define HINIC_API_CMD_DESC_MGMT_BYPASS_MASK 0x1
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#define HINIC_API_CMD_DESC_DEST_MASK 0x1F
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#define HINIC_API_CMD_DESC_SIZE_MASK 0x7FF
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#define HINIC_API_CMD_DESC_XOR_CHKSUM_MASK 0xFF
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#define HINIC_API_CMD_DESC_SET(val, member) \
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((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \
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HINIC_API_CMD_DESC_##member##_SHIFT)
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#define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT 16
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#define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_MASK 0xFF
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#define HINIC_API_CMD_STATUS_HEADER_GET(val, member) \
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(((val) >> HINIC_API_CMD_STATUS_HEADER_##member##_SHIFT) & \
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HINIC_API_CMD_STATUS_HEADER_##member##_MASK)
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#define HINIC_API_CMD_STATUS_CONS_IDX_SHIFT 0
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#define HINIC_API_CMD_STATUS_FSM_SHIFT 24
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#define HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT 28
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#define HINIC_API_CMD_STATUS_CPLD_ERR_SHIFT 30
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#define HINIC_API_CMD_STATUS_CONS_IDX_MASK 0xFFFFFF
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#define HINIC_API_CMD_STATUS_FSM_MASK 0xFU
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#define HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK 0x3
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#define HINIC_API_CMD_STATUS_CPLD_ERR_MASK 0x1U
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#define HINIC_API_CMD_STATUS_GET(val, member) \
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(((val) >> HINIC_API_CMD_STATUS_##member##_SHIFT) & \
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HINIC_API_CMD_STATUS_##member##_MASK)
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enum hinic_api_cmd_chain_type {
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HINIC_API_CMD_WRITE_TO_MGMT_CPU = 2,
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HINIC_API_CMD_MAX,
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};
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struct hinic_api_cmd_chain_attr {
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struct hinic_hwif *hwif;
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enum hinic_api_cmd_chain_type chain_type;
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u32 num_cells;
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u16 cell_size;
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};
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struct hinic_api_cmd_status {
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u64 header;
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u32 status;
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u32 rsvd0;
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u32 rsvd1;
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u32 rsvd2;
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u64 rsvd3;
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};
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/* HW struct */
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struct hinic_api_cmd_cell {
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u64 ctrl;
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/* address is 64 bit in HW struct */
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u64 next_cell_paddr;
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u64 desc;
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/* HW struct */
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union {
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struct {
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u64 hw_cmd_paddr;
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} write;
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struct {
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u64 hw_wb_resp_paddr;
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u64 hw_cmd_paddr;
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} read;
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};
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};
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struct hinic_api_cmd_cell_ctxt {
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dma_addr_t cell_paddr;
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struct hinic_api_cmd_cell *cell_vaddr;
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dma_addr_t api_cmd_paddr;
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u8 *api_cmd_vaddr;
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};
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struct hinic_api_cmd_chain {
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struct hinic_hwif *hwif;
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enum hinic_api_cmd_chain_type chain_type;
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u32 num_cells;
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u16 cell_size;
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/* HW members in 24 bit format */
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u32 prod_idx;
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u32 cons_idx;
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struct semaphore sem;
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struct hinic_api_cmd_cell_ctxt *cell_ctxt;
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dma_addr_t wb_status_paddr;
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struct hinic_api_cmd_status *wb_status;
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dma_addr_t head_cell_paddr;
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struct hinic_api_cmd_cell *head_node;
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struct hinic_api_cmd_cell *curr_node;
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};
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int hinic_api_cmd_write(struct hinic_api_cmd_chain *chain,
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enum hinic_node_id dest, u8 *cmd, u16 size);
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int hinic_api_cmd_init(struct hinic_api_cmd_chain **chain,
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struct hinic_hwif *hwif);
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void hinic_api_cmd_free(struct hinic_api_cmd_chain **chain);
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#endif
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