233 lines
6.6 KiB
C
233 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef HINIC_HW_QP_H
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#define HINIC_HW_QP_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/sizes.h>
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#include <linux/pci.h>
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#include <linux/skbuff.h>
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#include "hinic_common.h"
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#include "hinic_hw_if.h"
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#include "hinic_hw_wqe.h"
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#include "hinic_hw_wq.h"
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#include "hinic_hw_qp_ctxt.h"
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#define HINIC_SQ_DB_INFO_PI_HI_SHIFT 0
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#define HINIC_SQ_DB_INFO_QID_SHIFT 8
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#define HINIC_SQ_DB_INFO_PATH_SHIFT 23
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#define HINIC_SQ_DB_INFO_COS_SHIFT 24
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#define HINIC_SQ_DB_INFO_TYPE_SHIFT 27
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#define HINIC_SQ_DB_INFO_PI_HI_MASK 0xFF
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#define HINIC_SQ_DB_INFO_QID_MASK 0x3FF
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#define HINIC_SQ_DB_INFO_PATH_MASK 0x1
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#define HINIC_SQ_DB_INFO_COS_MASK 0x7
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#define HINIC_SQ_DB_INFO_TYPE_MASK 0x1F
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#define HINIC_SQ_DB_INFO_SET(val, member) \
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(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \
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<< HINIC_SQ_DB_INFO_##member##_SHIFT)
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#define HINIC_SQ_WQEBB_SIZE 64
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#define HINIC_RQ_WQEBB_SIZE 32
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#define HINIC_SQ_PAGE_SIZE SZ_256K
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#define HINIC_RQ_PAGE_SIZE SZ_256K
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#define HINIC_SQ_DEPTH SZ_4K
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#define HINIC_RQ_DEPTH SZ_4K
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#define HINIC_MAX_QUEUE_DEPTH SZ_4K
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#define HINIC_MIN_QUEUE_DEPTH 128
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/* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
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#define HINIC_RX_BUF_SZ 2048
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#define HINIC_RX_BUF_SZ_IDX HINIC_RX_BUF_SZ_2048_IDX
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#define HINIC_MIN_TX_WQE_SIZE(wq) \
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ALIGN(HINIC_SQ_WQE_SIZE(1), (wq)->wqebb_size)
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#define HINIC_MIN_TX_NUM_WQEBBS(sq) \
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(HINIC_MIN_TX_WQE_SIZE((sq)->wq) / (sq)->wq->wqebb_size)
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enum hinic_rx_buf_sz_idx {
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HINIC_RX_BUF_SZ_32_IDX,
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HINIC_RX_BUF_SZ_64_IDX,
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HINIC_RX_BUF_SZ_96_IDX,
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HINIC_RX_BUF_SZ_128_IDX,
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HINIC_RX_BUF_SZ_192_IDX,
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HINIC_RX_BUF_SZ_256_IDX,
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HINIC_RX_BUF_SZ_384_IDX,
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HINIC_RX_BUF_SZ_512_IDX,
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HINIC_RX_BUF_SZ_768_IDX,
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HINIC_RX_BUF_SZ_1024_IDX,
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HINIC_RX_BUF_SZ_1536_IDX,
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HINIC_RX_BUF_SZ_2048_IDX,
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HINIC_RX_BUF_SZ_3072_IDX,
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HINIC_RX_BUF_SZ_4096_IDX,
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HINIC_RX_BUF_SZ_8192_IDX,
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HINIC_RX_BUF_SZ_16384_IDX,
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};
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struct hinic_sq {
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struct hinic_hwif *hwif;
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struct hinic_wq *wq;
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u16 qid;
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u32 irq;
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u16 msix_entry;
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void *hw_ci_addr;
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dma_addr_t hw_ci_dma_addr;
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void __iomem *db_base;
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struct sk_buff **saved_skb;
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struct hinic_debug_priv *dbg;
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};
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struct hinic_rq {
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struct hinic_hwif *hwif;
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struct hinic_wq *wq;
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u16 qid;
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struct cpumask affinity_mask;
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u32 irq;
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u16 msix_entry;
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size_t buf_sz;
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struct sk_buff **saved_skb;
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struct hinic_rq_cqe **cqe;
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dma_addr_t *cqe_dma;
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u16 *pi_virt_addr;
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dma_addr_t pi_dma_addr;
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struct hinic_debug_priv *dbg;
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};
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struct hinic_qp {
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struct hinic_sq sq;
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struct hinic_rq rq;
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u16 q_id;
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};
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void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
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enum hinic_qp_ctxt_type ctxt_type,
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u16 num_queues, u16 max_queues);
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void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
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struct hinic_sq *sq, u16 global_qid);
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void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
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struct hinic_rq *rq, u16 global_qid);
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int hinic_init_sq(struct hinic_sq *sq, struct hinic_hwif *hwif,
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struct hinic_wq *wq, struct msix_entry *entry, void *ci_addr,
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dma_addr_t ci_dma_addr, void __iomem *db_base);
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void hinic_clean_sq(struct hinic_sq *sq);
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int hinic_init_rq(struct hinic_rq *rq, struct hinic_hwif *hwif,
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struct hinic_wq *wq, struct msix_entry *entry);
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void hinic_clean_rq(struct hinic_rq *rq);
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int hinic_get_sq_free_wqebbs(struct hinic_sq *sq);
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int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);
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void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);
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void hinic_task_set_outter_l3(struct hinic_sq_task *task,
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enum hinic_l3_offload_type l3_type,
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u32 network_len);
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void hinic_task_set_inner_l3(struct hinic_sq_task *task,
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enum hinic_l3_offload_type l3_type,
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u32 network_len);
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void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
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enum hinic_l4_tunnel_type l4_type,
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u32 tunnel_len);
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void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
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u32 *queue_info,
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enum hinic_l4_offload_type l4_offload,
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u32 l4_len, u32 offset);
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void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
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u32 *queue_info,
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enum hinic_l4_offload_type l4_offload,
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u32 l4_len,
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u32 offset, u32 ip_ident, u32 mss);
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void hinic_sq_prepare_wqe(struct hinic_sq *sq, struct hinic_sq_wqe *wqe,
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struct hinic_sge *sges, int nr_sges);
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void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
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unsigned int cos);
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struct hinic_sq_wqe *hinic_sq_get_wqe(struct hinic_sq *sq,
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unsigned int wqe_size, u16 *prod_idx);
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void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);
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void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
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struct hinic_sq_wqe *wqe, struct sk_buff *skb,
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unsigned int wqe_size);
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struct hinic_sq_wqe *hinic_sq_read_wqe(struct hinic_sq *sq,
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struct sk_buff **skb,
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unsigned int wqe_size, u16 *cons_idx);
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struct hinic_sq_wqe *hinic_sq_read_wqebb(struct hinic_sq *sq,
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struct sk_buff **skb,
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unsigned int *wqe_size, u16 *cons_idx);
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void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size);
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void hinic_sq_get_sges(struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
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int nr_sges);
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struct hinic_rq_wqe *hinic_rq_get_wqe(struct hinic_rq *rq,
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unsigned int wqe_size, u16 *prod_idx);
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void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
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struct hinic_rq_wqe *wqe, struct sk_buff *skb);
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struct hinic_rq_wqe *hinic_rq_read_wqe(struct hinic_rq *rq,
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unsigned int wqe_size,
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struct sk_buff **skb, u16 *cons_idx);
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struct hinic_rq_wqe *hinic_rq_read_next_wqe(struct hinic_rq *rq,
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unsigned int wqe_size,
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struct sk_buff **skb,
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u16 *cons_idx);
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void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
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unsigned int wqe_size);
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void hinic_rq_get_sge(struct hinic_rq *rq, struct hinic_rq_wqe *wqe,
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u16 cons_idx, struct hinic_sge *sge);
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void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
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struct hinic_rq_wqe *wqe, struct hinic_sge *sge);
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void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx);
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#endif
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