616 lines
15 KiB
C
616 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#include "e1000.h"
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/**
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* e1000_raise_eec_clk - Raise EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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*
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* Enable/Raise the EEPROM clock bit.
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**/
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static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
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{
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*eecd = *eecd | E1000_EECD_SK;
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ew32(EECD, *eecd);
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e1e_flush();
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udelay(hw->nvm.delay_usec);
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}
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/**
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* e1000_lower_eec_clk - Lower EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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*
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* Clear/Lower the EEPROM clock bit.
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**/
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static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
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{
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*eecd = *eecd & ~E1000_EECD_SK;
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ew32(EECD, *eecd);
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e1e_flush();
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udelay(hw->nvm.delay_usec);
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}
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/**
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* e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
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* @hw: pointer to the HW structure
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* @data: data to send to the EEPROM
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* @count: number of bits to shift out
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*
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* We need to shift 'count' bits out to the EEPROM. So, the value in the
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* "data" parameter will be shifted out to the EEPROM one bit at a time.
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* In order to do this, "data" must be broken down into bits.
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**/
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static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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u32 mask;
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mask = BIT(count - 1);
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if (nvm->type == e1000_nvm_eeprom_spi)
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eecd |= E1000_EECD_DO;
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do {
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eecd &= ~E1000_EECD_DI;
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if (data & mask)
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eecd |= E1000_EECD_DI;
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ew32(EECD, eecd);
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e1e_flush();
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udelay(nvm->delay_usec);
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e1000_raise_eec_clk(hw, &eecd);
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e1000_lower_eec_clk(hw, &eecd);
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mask >>= 1;
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} while (mask);
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eecd &= ~E1000_EECD_DI;
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ew32(EECD, eecd);
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}
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/**
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* e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
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* @hw: pointer to the HW structure
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* @count: number of bits to shift in
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*
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* In order to read a register from the EEPROM, we need to shift 'count' bits
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* in from the EEPROM. Bits are "shifted in" by raising the clock input to
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* the EEPROM (setting the SK bit), and then reading the value of the data out
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* "DO" bit. During this "shifting in" process the data in "DI" bit should
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* always be clear.
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**/
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static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
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{
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u32 eecd;
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u32 i;
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u16 data;
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eecd = er32(EECD);
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eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
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data = 0;
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for (i = 0; i < count; i++) {
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data <<= 1;
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e1000_raise_eec_clk(hw, &eecd);
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eecd = er32(EECD);
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eecd &= ~E1000_EECD_DI;
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if (eecd & E1000_EECD_DO)
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data |= 1;
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e1000_lower_eec_clk(hw, &eecd);
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}
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return data;
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}
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/**
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* e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
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* @hw: pointer to the HW structure
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* @ee_reg: EEPROM flag for polling
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*
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* Polls the EEPROM status bit for either read or write completion based
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* upon the value of 'ee_reg'.
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**/
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s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
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{
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u32 attempts = 100000;
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u32 i, reg = 0;
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for (i = 0; i < attempts; i++) {
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if (ee_reg == E1000_NVM_POLL_READ)
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reg = er32(EERD);
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else
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reg = er32(EEWR);
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if (reg & E1000_NVM_RW_REG_DONE)
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return 0;
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udelay(5);
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}
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return -E1000_ERR_NVM;
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}
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/**
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* e1000e_acquire_nvm - Generic request for access to EEPROM
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* @hw: pointer to the HW structure
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*
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* Set the EEPROM access request bit and wait for EEPROM access grant bit.
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* Return successful if access grant bit set, else clear the request for
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* EEPROM access and return -E1000_ERR_NVM (-1).
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**/
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s32 e1000e_acquire_nvm(struct e1000_hw *hw)
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{
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u32 eecd = er32(EECD);
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s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
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ew32(EECD, eecd | E1000_EECD_REQ);
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eecd = er32(EECD);
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while (timeout) {
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if (eecd & E1000_EECD_GNT)
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break;
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udelay(5);
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eecd = er32(EECD);
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timeout--;
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}
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if (!timeout) {
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eecd &= ~E1000_EECD_REQ;
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ew32(EECD, eecd);
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e_dbg("Could not acquire NVM grant\n");
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return -E1000_ERR_NVM;
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}
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return 0;
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}
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/**
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* e1000_standby_nvm - Return EEPROM to standby state
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* @hw: pointer to the HW structure
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*
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* Return the EEPROM to a standby state.
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**/
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static void e1000_standby_nvm(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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if (nvm->type == e1000_nvm_eeprom_spi) {
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/* Toggle CS to flush commands */
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eecd |= E1000_EECD_CS;
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ew32(EECD, eecd);
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e1e_flush();
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udelay(nvm->delay_usec);
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eecd &= ~E1000_EECD_CS;
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ew32(EECD, eecd);
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e1e_flush();
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udelay(nvm->delay_usec);
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}
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}
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/**
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* e1000_stop_nvm - Terminate EEPROM command
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* @hw: pointer to the HW structure
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*
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* Terminates the current command by inverting the EEPROM's chip select pin.
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**/
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static void e1000_stop_nvm(struct e1000_hw *hw)
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{
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u32 eecd;
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eecd = er32(EECD);
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if (hw->nvm.type == e1000_nvm_eeprom_spi) {
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/* Pull CS high */
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eecd |= E1000_EECD_CS;
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e1000_lower_eec_clk(hw, &eecd);
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}
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}
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/**
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* e1000e_release_nvm - Release exclusive access to EEPROM
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* @hw: pointer to the HW structure
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*
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* Stop any current commands to the EEPROM and clear the EEPROM request bit.
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**/
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void e1000e_release_nvm(struct e1000_hw *hw)
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{
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u32 eecd;
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e1000_stop_nvm(hw);
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eecd = er32(EECD);
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eecd &= ~E1000_EECD_REQ;
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ew32(EECD, eecd);
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}
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/**
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* e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
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* @hw: pointer to the HW structure
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*
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* Setups the EEPROM for reading and writing.
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**/
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static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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u8 spi_stat_reg;
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if (nvm->type == e1000_nvm_eeprom_spi) {
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u16 timeout = NVM_MAX_RETRY_SPI;
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/* Clear SK and CS */
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eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
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ew32(EECD, eecd);
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e1e_flush();
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udelay(1);
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/* Read "Status Register" repeatedly until the LSB is cleared.
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* The EEPROM will signal that the command has been completed
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* by clearing bit 0 of the internal status register. If it's
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* not cleared within 'timeout', then error out.
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*/
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while (timeout) {
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e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
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hw->nvm.opcode_bits);
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spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
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if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
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break;
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udelay(5);
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e1000_standby_nvm(hw);
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timeout--;
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}
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if (!timeout) {
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e_dbg("SPI NVM Status error\n");
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return -E1000_ERR_NVM;
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}
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}
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return 0;
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}
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/**
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* e1000e_read_nvm_eerd - Reads EEPROM using EERD register
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* @hw: pointer to the HW structure
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* @offset: offset of word in the EEPROM to read
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* @words: number of words to read
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* @data: word read from the EEPROM
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*
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* Reads a 16 bit word from the EEPROM using the EERD register.
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**/
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s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 i, eerd = 0;
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s32 ret_val = 0;
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/* A check for invalid values: offset too large, too many words,
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* too many words for the offset, and not enough words.
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*/
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
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(words == 0)) {
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e_dbg("nvm parameter(s) out of bounds\n");
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return -E1000_ERR_NVM;
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}
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for (i = 0; i < words; i++) {
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eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
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E1000_NVM_RW_REG_START;
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ew32(EERD, eerd);
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ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
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if (ret_val) {
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e_dbg("NVM read error: %d\n", ret_val);
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break;
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}
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data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
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}
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return ret_val;
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}
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/**
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* e1000e_write_nvm_spi - Write to EEPROM using SPI
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* @hw: pointer to the HW structure
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* @offset: offset within the EEPROM to be written to
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* @words: number of words to write
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* @data: 16 bit word(s) to be written to the EEPROM
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*
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* Writes data to EEPROM at offset using SPI interface.
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*
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* If e1000e_update_nvm_checksum is not called after this function , the
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* EEPROM will most likely contain an invalid checksum.
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**/
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s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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s32 ret_val = -E1000_ERR_NVM;
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u16 widx = 0;
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/* A check for invalid values: offset too large, too many words,
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* and not enough words.
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*/
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
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(words == 0)) {
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e_dbg("nvm parameter(s) out of bounds\n");
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return -E1000_ERR_NVM;
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}
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while (widx < words) {
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u8 write_opcode = NVM_WRITE_OPCODE_SPI;
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ret_val = nvm->ops.acquire(hw);
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if (ret_val)
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return ret_val;
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ret_val = e1000_ready_nvm_eeprom(hw);
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if (ret_val) {
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nvm->ops.release(hw);
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return ret_val;
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}
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e1000_standby_nvm(hw);
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/* Send the WRITE ENABLE command (8 bit opcode) */
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e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
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nvm->opcode_bits);
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e1000_standby_nvm(hw);
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/* Some SPI eeproms use the 8th address bit embedded in the
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* opcode
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*/
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if ((nvm->address_bits == 8) && (offset >= 128))
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write_opcode |= NVM_A8_OPCODE_SPI;
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/* Send the Write command (8-bit opcode + addr) */
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e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
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e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
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nvm->address_bits);
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/* Loop to allow for up to whole page write of eeprom */
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while (widx < words) {
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u16 word_out = data[widx];
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word_out = (word_out >> 8) | (word_out << 8);
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e1000_shift_out_eec_bits(hw, word_out, 16);
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widx++;
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if ((((offset + widx) * 2) % nvm->page_size) == 0) {
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e1000_standby_nvm(hw);
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break;
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}
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}
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usleep_range(10000, 11000);
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nvm->ops.release(hw);
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}
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return ret_val;
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}
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/**
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* e1000_read_pba_string_generic - Read device part number
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* @hw: pointer to the HW structure
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* @pba_num: pointer to device part number
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* @pba_num_size: size of part number buffer
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*
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* Reads the product board assembly (PBA) number from the EEPROM and stores
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* the value in pba_num.
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**/
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s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
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u32 pba_num_size)
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{
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s32 ret_val;
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u16 nvm_data;
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u16 pba_ptr;
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u16 offset;
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u16 length;
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if (pba_num == NULL) {
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e_dbg("PBA string buffer was null\n");
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return -E1000_ERR_INVALID_ARGUMENT;
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}
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ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
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if (ret_val) {
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e_dbg("NVM Read Error\n");
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return ret_val;
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}
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ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
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if (ret_val) {
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e_dbg("NVM Read Error\n");
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return ret_val;
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}
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/* if nvm_data is not ptr guard the PBA must be in legacy format which
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* means pba_ptr is actually our second data word for the PBA number
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* and we can decode it into an ascii string
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*/
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if (nvm_data != NVM_PBA_PTR_GUARD) {
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e_dbg("NVM PBA number is not stored as string\n");
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/* make sure callers buffer is big enough to store the PBA */
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if (pba_num_size < E1000_PBANUM_LENGTH) {
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e_dbg("PBA string buffer too small\n");
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return E1000_ERR_NO_SPACE;
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}
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/* extract hex string from data and pba_ptr */
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pba_num[0] = (nvm_data >> 12) & 0xF;
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pba_num[1] = (nvm_data >> 8) & 0xF;
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pba_num[2] = (nvm_data >> 4) & 0xF;
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pba_num[3] = nvm_data & 0xF;
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pba_num[4] = (pba_ptr >> 12) & 0xF;
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pba_num[5] = (pba_ptr >> 8) & 0xF;
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pba_num[6] = '-';
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pba_num[7] = 0;
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pba_num[8] = (pba_ptr >> 4) & 0xF;
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pba_num[9] = pba_ptr & 0xF;
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/* put a null character on the end of our string */
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pba_num[10] = '\0';
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/* switch all the data but the '-' to hex char */
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for (offset = 0; offset < 10; offset++) {
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if (pba_num[offset] < 0xA)
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pba_num[offset] += '0';
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else if (pba_num[offset] < 0x10)
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pba_num[offset] += 'A' - 0xA;
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}
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return 0;
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}
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ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
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if (ret_val) {
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e_dbg("NVM Read Error\n");
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return ret_val;
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}
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if (length == 0xFFFF || length == 0) {
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e_dbg("NVM PBA number section invalid length\n");
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return -E1000_ERR_NVM_PBA_SECTION;
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}
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/* check if pba_num buffer is big enough */
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if (pba_num_size < (((u32)length * 2) - 1)) {
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e_dbg("PBA string buffer too small\n");
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return -E1000_ERR_NO_SPACE;
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}
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/* trim pba length from start of string */
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pba_ptr++;
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length--;
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for (offset = 0; offset < length; offset++) {
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ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
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if (ret_val) {
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e_dbg("NVM Read Error\n");
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return ret_val;
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}
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pba_num[offset * 2] = (u8)(nvm_data >> 8);
|
|
pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
|
|
}
|
|
pba_num[offset * 2] = '\0';
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_mac_addr_generic - Read device MAC address
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reads the device MAC address from the EEPROM and stores the value.
|
|
* Since devices with two ports use the same EEPROM, we increment the
|
|
* last bit in the MAC address for the second port.
|
|
**/
|
|
s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
|
|
{
|
|
u32 rar_high;
|
|
u32 rar_low;
|
|
u16 i;
|
|
|
|
rar_high = er32(RAH(0));
|
|
rar_low = er32(RAL(0));
|
|
|
|
for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
|
|
hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
|
|
|
|
for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
|
|
hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
|
|
|
|
for (i = 0; i < ETH_ALEN; i++)
|
|
hw->mac.addr[i] = hw->mac.perm_addr[i];
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
|
|
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
|
|
**/
|
|
s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
u16 checksum = 0;
|
|
u16 i, nvm_data;
|
|
|
|
for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
|
|
ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
|
|
if (ret_val) {
|
|
e_dbg("NVM Read Error\n");
|
|
return ret_val;
|
|
}
|
|
checksum += nvm_data;
|
|
}
|
|
|
|
if (checksum != (u16)NVM_SUM) {
|
|
e_dbg("NVM Checksum Invalid\n");
|
|
return -E1000_ERR_NVM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* e1000e_update_nvm_checksum_generic - Update EEPROM checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
|
|
* up to the checksum. Then calculates the EEPROM checksum and writes the
|
|
* value to the EEPROM.
|
|
**/
|
|
s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
u16 checksum = 0;
|
|
u16 i, nvm_data;
|
|
|
|
for (i = 0; i < NVM_CHECKSUM_REG; i++) {
|
|
ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
|
|
if (ret_val) {
|
|
e_dbg("NVM Read Error while updating checksum.\n");
|
|
return ret_val;
|
|
}
|
|
checksum += nvm_data;
|
|
}
|
|
checksum = (u16)NVM_SUM - checksum;
|
|
ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
|
|
if (ret_val)
|
|
e_dbg("NVM Write Error while updating checksum.\n");
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000e_reload_nvm_generic - Reloads EEPROM
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
|
|
* extended control register.
|
|
**/
|
|
void e1000e_reload_nvm_generic(struct e1000_hw *hw)
|
|
{
|
|
u32 ctrl_ext;
|
|
|
|
usleep_range(10, 20);
|
|
ctrl_ext = er32(CTRL_EXT);
|
|
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
|
|
ew32(CTRL_EXT, ctrl_ext);
|
|
e1e_flush();
|
|
}
|