465 lines
14 KiB
C
465 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021, Intel Corporation. */
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#ifndef _ICE_PTP_HW_H_
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#define _ICE_PTP_HW_H_
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enum ice_ptp_tmr_cmd {
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INIT_TIME,
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INIT_INCVAL,
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ADJ_TIME,
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ADJ_TIME_AT_TIME,
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READ_TIME
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};
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enum ice_ptp_serdes {
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ICE_PTP_SERDES_1G,
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ICE_PTP_SERDES_10G,
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ICE_PTP_SERDES_25G,
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ICE_PTP_SERDES_40G,
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ICE_PTP_SERDES_50G,
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ICE_PTP_SERDES_100G
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};
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enum ice_ptp_link_spd {
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ICE_PTP_LNK_SPD_1G,
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ICE_PTP_LNK_SPD_10G,
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ICE_PTP_LNK_SPD_25G,
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ICE_PTP_LNK_SPD_25G_RS,
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ICE_PTP_LNK_SPD_40G,
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ICE_PTP_LNK_SPD_50G,
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ICE_PTP_LNK_SPD_50G_RS,
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ICE_PTP_LNK_SPD_100G_RS,
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NUM_ICE_PTP_LNK_SPD /* Must be last */
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};
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enum ice_ptp_fec_mode {
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ICE_PTP_FEC_MODE_NONE,
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ICE_PTP_FEC_MODE_CLAUSE74,
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ICE_PTP_FEC_MODE_RS_FEC
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};
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/**
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* struct ice_time_ref_info_e822
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* @pll_freq: Frequency of PLL that drives timer ticks in Hz
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* @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
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* @pps_delay: propagation delay of the PPS output signal
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*
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* Characteristic information for the various TIME_REF sources possible in the
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* E822 devices
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*/
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struct ice_time_ref_info_e822 {
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u64 pll_freq;
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u64 nominal_incval;
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u8 pps_delay;
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};
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/**
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* struct ice_vernier_info_e822
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* @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
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* @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
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* @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
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* @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
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* @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
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* @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
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* @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
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* @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
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* @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
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* @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
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* @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
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*
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* Table of constants used during as part of the Vernier calibration of the Tx
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* and Rx timestamps. This includes frequency values used to compute TUs per
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* PAR/PCS clock cycle, and static delay values measured during hardware
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* design.
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*
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* Note that some values are not used for all link speeds, and the
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* P_REG_DESK_PAR* registers may represent different clock markers at
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* different link speeds, either the deskew marker for multi-lane link speeds
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* or the Reed Solomon gearbox marker for RS-FEC.
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*/
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struct ice_vernier_info_e822 {
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u32 tx_par_clk;
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u32 rx_par_clk;
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u32 tx_pcs_clk;
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u32 rx_pcs_clk;
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u32 tx_desk_rsgb_par;
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u32 rx_desk_rsgb_par;
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u32 tx_desk_rsgb_pcs;
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u32 rx_desk_rsgb_pcs;
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u32 tx_fixed_delay;
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u32 pmd_adj_divisor;
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u32 rx_fixed_delay;
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};
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/**
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* struct ice_cgu_pll_params_e822
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* @refclk_pre_div: Reference clock pre-divisor
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* @feedback_div: Feedback divisor
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* @frac_n_div: Fractional divisor
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* @post_pll_div: Post PLL divisor
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*
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* Clock Generation Unit parameters used to program the PLL based on the
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* selected TIME_REF frequency.
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*/
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struct ice_cgu_pll_params_e822 {
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u32 refclk_pre_div;
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u32 feedback_div;
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u32 frac_n_div;
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u32 post_pll_div;
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};
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extern const struct
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ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
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/* Table of constants related to possible TIME_REF sources */
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extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
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/* Table of constants for Vernier calibration on E822 */
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extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
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/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
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* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
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*/
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#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
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/* Device agnostic functions */
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u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
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bool ice_ptp_lock(struct ice_hw *hw);
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void ice_ptp_unlock(struct ice_hw *hw);
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int ice_ptp_init_time(struct ice_hw *hw, u64 time);
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int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
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int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
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int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
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int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
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int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
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void ice_ptp_reset_ts_memory(struct ice_hw *hw);
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int ice_ptp_init_phc(struct ice_hw *hw);
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int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
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/* E822 family functions */
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int ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
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int ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val);
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int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
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int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
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int ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time);
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void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);
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/**
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* ice_e822_time_ref - Get the current TIME_REF from capabilities
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* @hw: pointer to the HW structure
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*
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* Returns the current TIME_REF from the capabilities structure.
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*/
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static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
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{
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return hw->func_caps.ts_func_info.time_ref;
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}
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/**
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* ice_set_e822_time_ref - Set new TIME_REF
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* @hw: pointer to the HW structure
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* @time_ref: new TIME_REF to set
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*
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* Update the TIME_REF in the capabilities structure in response to some
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* change, such as an update to the CGU registers.
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*/
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static inline void
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ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
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{
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hw->func_caps.ts_func_info.time_ref = time_ref;
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}
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static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
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{
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return e822_time_ref[time_ref].pll_freq;
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}
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static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
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{
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return e822_time_ref[time_ref].nominal_incval;
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}
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static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
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{
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return e822_time_ref[time_ref].pps_delay;
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}
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/* E822 Vernier calibration functions */
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int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
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int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
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int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
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int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
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/* E810 family functions */
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int ice_ptp_init_phy_e810(struct ice_hw *hw);
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int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
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int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
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int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
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bool ice_is_pca9575_present(struct ice_hw *hw);
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#define PFTSYN_SEM_BYTES 4
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#define ICE_PTP_CLOCK_INDEX_0 0x00
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#define ICE_PTP_CLOCK_INDEX_1 0x01
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/* PHY timer commands */
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#define SEL_CPK_SRC 8
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#define SEL_PHY_SRC 3
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/* Time Sync command Definitions */
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#define GLTSYN_CMD_INIT_TIME BIT(0)
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#define GLTSYN_CMD_INIT_INCVAL BIT(1)
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#define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
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#define GLTSYN_CMD_ADJ_TIME BIT(2)
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#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
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#define GLTSYN_CMD_READ_TIME BIT(7)
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/* PHY port Time Sync command definitions */
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#define PHY_CMD_INIT_TIME BIT(0)
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#define PHY_CMD_INIT_INCVAL BIT(1)
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#define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
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#define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
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#define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
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#define TS_CMD_MASK_E810 0xFF
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#define TS_CMD_MASK 0xF
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#define SYNC_EXEC_CMD 0x3
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/* Macros to derive port low and high addresses on both quads */
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#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
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#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
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#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
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#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
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/* PHY QUAD register base addresses */
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#define Q_0_BASE 0x94000
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#define Q_1_BASE 0x114000
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/* Timestamp memory reset registers */
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#define Q_REG_TS_CTRL 0x618
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#define Q_REG_TS_CTRL_S 0
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#define Q_REG_TS_CTRL_M BIT(0)
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/* Timestamp availability status registers */
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#define Q_REG_TX_MEMORY_STATUS_L 0xCF0
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#define Q_REG_TX_MEMORY_STATUS_U 0xCF4
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/* Tx FIFO status registers */
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#define Q_REG_FIFO23_STATUS 0xCF8
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#define Q_REG_FIFO01_STATUS 0xCFC
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#define Q_REG_FIFO02_S 0
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#define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
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#define Q_REG_FIFO13_S 10
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#define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
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/* Interrupt control Config registers */
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#define Q_REG_TX_MEM_GBL_CFG 0xC08
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#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
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#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
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#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
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#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
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#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
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#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
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#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
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#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
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/* Tx Timestamp data registers */
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#define Q_REG_TX_MEMORY_BANK_START 0xA00
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/* PHY port register base addresses */
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#define P_0_BASE 0x80000
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#define P_4_BASE 0x106000
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/* Timestamp init registers */
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#define P_REG_RX_TIMER_INC_PRE_L 0x46C
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#define P_REG_RX_TIMER_INC_PRE_U 0x470
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#define P_REG_TX_TIMER_INC_PRE_L 0x44C
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#define P_REG_TX_TIMER_INC_PRE_U 0x450
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/* Timestamp match and adjust target registers */
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#define P_REG_RX_TIMER_CNT_ADJ_L 0x474
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#define P_REG_RX_TIMER_CNT_ADJ_U 0x478
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#define P_REG_TX_TIMER_CNT_ADJ_L 0x454
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#define P_REG_TX_TIMER_CNT_ADJ_U 0x458
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/* Timestamp capture registers */
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#define P_REG_RX_CAPTURE_L 0x4D8
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#define P_REG_RX_CAPTURE_U 0x4DC
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#define P_REG_TX_CAPTURE_L 0x4B4
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#define P_REG_TX_CAPTURE_U 0x4B8
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/* Timestamp PHY incval registers */
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#define P_REG_TIMETUS_L 0x410
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#define P_REG_TIMETUS_U 0x414
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#define P_REG_40B_LOW_M 0xFF
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#define P_REG_40B_HIGH_S 8
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/* PHY window length registers */
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#define P_REG_WL 0x40C
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#define PTP_VERNIER_WL 0x111ed
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/* PHY start registers */
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#define P_REG_PS 0x408
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#define P_REG_PS_START_S 0
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#define P_REG_PS_START_M BIT(0)
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#define P_REG_PS_BYPASS_MODE_S 1
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#define P_REG_PS_BYPASS_MODE_M BIT(1)
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#define P_REG_PS_ENA_CLK_S 2
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#define P_REG_PS_ENA_CLK_M BIT(2)
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#define P_REG_PS_LOAD_OFFSET_S 3
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#define P_REG_PS_LOAD_OFFSET_M BIT(3)
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#define P_REG_PS_SFT_RESET_S 11
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#define P_REG_PS_SFT_RESET_M BIT(11)
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/* PHY offset valid registers */
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#define P_REG_TX_OV_STATUS 0x4D4
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#define P_REG_TX_OV_STATUS_OV_S 0
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#define P_REG_TX_OV_STATUS_OV_M BIT(0)
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#define P_REG_RX_OV_STATUS 0x4F8
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#define P_REG_RX_OV_STATUS_OV_S 0
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#define P_REG_RX_OV_STATUS_OV_M BIT(0)
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/* PHY offset ready registers */
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#define P_REG_TX_OR 0x45C
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#define P_REG_RX_OR 0x47C
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/* PHY total offset registers */
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#define P_REG_TOTAL_RX_OFFSET_L 0x460
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#define P_REG_TOTAL_RX_OFFSET_U 0x464
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#define P_REG_TOTAL_TX_OFFSET_L 0x440
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#define P_REG_TOTAL_TX_OFFSET_U 0x444
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/* Timestamp PAR/PCS registers */
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#define P_REG_UIX66_10G_40G_L 0x480
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#define P_REG_UIX66_10G_40G_U 0x484
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#define P_REG_UIX66_25G_100G_L 0x488
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#define P_REG_UIX66_25G_100G_U 0x48C
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#define P_REG_DESK_PAR_RX_TUS_L 0x490
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#define P_REG_DESK_PAR_RX_TUS_U 0x494
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#define P_REG_DESK_PAR_TX_TUS_L 0x498
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#define P_REG_DESK_PAR_TX_TUS_U 0x49C
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#define P_REG_DESK_PCS_RX_TUS_L 0x4A0
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#define P_REG_DESK_PCS_RX_TUS_U 0x4A4
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#define P_REG_DESK_PCS_TX_TUS_L 0x4A8
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#define P_REG_DESK_PCS_TX_TUS_U 0x4AC
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#define P_REG_PAR_RX_TUS_L 0x420
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#define P_REG_PAR_RX_TUS_U 0x424
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#define P_REG_PAR_TX_TUS_L 0x428
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#define P_REG_PAR_TX_TUS_U 0x42C
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#define P_REG_PCS_RX_TUS_L 0x430
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#define P_REG_PCS_RX_TUS_U 0x434
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#define P_REG_PCS_TX_TUS_L 0x438
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#define P_REG_PCS_TX_TUS_U 0x43C
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#define P_REG_PAR_RX_TIME_L 0x4F0
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#define P_REG_PAR_RX_TIME_U 0x4F4
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#define P_REG_PAR_TX_TIME_L 0x4CC
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#define P_REG_PAR_TX_TIME_U 0x4D0
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#define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
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#define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
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#define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
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#define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
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#define P_REG_LINK_SPEED 0x4FC
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#define P_REG_LINK_SPEED_SERDES_S 0
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#define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
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#define P_REG_LINK_SPEED_FEC_MODE_S 3
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#define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
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#define P_REG_LINK_SPEED_FEC_MODE(reg) \
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(((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
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P_REG_LINK_SPEED_FEC_MODE_S)
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/* PHY timestamp related registers */
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#define P_REG_PMD_ALIGNMENT 0x0FC
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#define P_REG_RX_80_TO_160_CNT 0x6FC
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#define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
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#define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
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#define P_REG_RX_40_TO_160_CNT 0x8FC
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#define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
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#define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
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/* Rx FIFO status registers */
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#define P_REG_RX_OV_FS 0x4F8
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#define P_REG_RX_OV_FS_FIFO_STATUS_S 2
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#define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
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/* Timestamp command registers */
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#define P_REG_TX_TMR_CMD 0x448
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#define P_REG_RX_TMR_CMD 0x468
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/* E810 timesync enable register */
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#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
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/* E810 shadow init time registers */
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#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
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#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
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/* E810 shadow time adjust registers */
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#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
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#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
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/* E810 timer command register */
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#define ETH_GLTSYN_CMD 0x03000344
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/* Source timer incval macros */
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#define INCVAL_HIGH_M 0xFF
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/* Timestamp block macros */
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#define TS_VALID BIT(0)
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#define TS_LOW_M 0xFFFFFFFF
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#define TS_HIGH_M 0xFF
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#define TS_HIGH_S 32
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#define TS_PHY_LOW_M 0xFF
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#define TS_PHY_HIGH_M 0xFFFFFFFF
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#define TS_PHY_HIGH_S 8
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#define BYTES_PER_IDX_ADDR_L_U 8
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#define BYTES_PER_IDX_ADDR_L 4
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/* Tx timestamp low latency read definitions */
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#define TS_LL_READ_RETRIES 200
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#define TS_LL_READ_TS_HIGH GENMASK(23, 16)
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#define TS_LL_READ_TS_IDX GENMASK(29, 24)
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#define TS_LL_READ_TS BIT(31)
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/* Internal PHY timestamp address */
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#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
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#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
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BYTES_PER_IDX_ADDR_L))
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/* External PHY timestamp address */
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#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
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((idx) * BYTES_PER_IDX_ADDR_L_U))
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#define LOW_TX_MEMORY_BANK_START 0x03090000
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#define HIGH_TX_MEMORY_BANK_START 0x03090004
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/* E810T SMA controller pin control */
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#define ICE_SMA1_DIR_EN_E810T BIT(4)
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#define ICE_SMA1_TX_EN_E810T BIT(5)
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#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
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#define ICE_SMA2_DIR_EN_E810T BIT(6)
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#define ICE_SMA2_TX_EN_E810T BIT(7)
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#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
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ICE_SMA1_TX_EN_E810T)
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#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
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ICE_SMA2_DIR_EN_E810T | \
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ICE_SMA2_TX_EN_E810T)
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#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
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ICE_SMA2_MASK_E810T)
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#define ICE_SMA_MIN_BIT_E810T 3
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#define ICE_SMA_MAX_BIT_E810T 7
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#define ICE_PCA9575_P1_OFFSET 8
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/* E810T PCA9575 IO controller registers */
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#define ICE_PCA9575_P0_IN 0x0
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/* E810T PCA9575 IO controller pin control */
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#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
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#endif /* _ICE_PTP_HW_H_ */
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