282 lines
6.7 KiB
C
282 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2022 Lorenzo Bianconi <lorenzo@kernel.org> */
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#ifndef __MTK_WED_WO_H
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#define __MTK_WED_WO_H
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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struct mtk_wed_hw;
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struct mtk_wed_mcu_hdr {
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/* DW0 */
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u8 version;
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u8 cmd;
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__le16 length;
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/* DW1 */
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__le16 seq;
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__le16 flag;
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/* DW2 */
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__le32 status;
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/* DW3 */
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u8 rsv[20];
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};
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struct mtk_wed_wo_log_info {
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__le32 sn;
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__le32 total;
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__le32 rro;
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__le32 mod;
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};
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enum mtk_wed_wo_event {
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MTK_WED_WO_EVT_LOG_DUMP = 0x1,
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MTK_WED_WO_EVT_PROFILING = 0x2,
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MTK_WED_WO_EVT_RXCNT_INFO = 0x3,
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};
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#define MTK_WED_MODULE_ID_WO 1
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#define MTK_FW_DL_TIMEOUT 4000000 /* us */
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#define MTK_WOCPU_TIMEOUT 2000000 /* us */
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enum {
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MTK_WED_WARP_CMD_FLAG_RSP = BIT(0),
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MTK_WED_WARP_CMD_FLAG_NEED_RSP = BIT(1),
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MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2),
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};
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#define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050
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#define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20
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#define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1
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enum {
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MTK_WED_WO_REGION_EMI,
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MTK_WED_WO_REGION_ILM,
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MTK_WED_WO_REGION_DATA,
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MTK_WED_WO_REGION_BOOT,
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__MTK_WED_WO_REGION_MAX,
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};
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enum mtk_wed_wo_state {
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MTK_WED_WO_STATE_UNDEFINED,
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MTK_WED_WO_STATE_INIT,
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MTK_WED_WO_STATE_ENABLE,
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MTK_WED_WO_STATE_DISABLE,
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MTK_WED_WO_STATE_HALT,
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MTK_WED_WO_STATE_GATING,
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MTK_WED_WO_STATE_SER_RESET,
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MTK_WED_WO_STATE_WF_RESET,
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};
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enum mtk_wed_wo_done_state {
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MTK_WED_WOIF_UNDEFINED,
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MTK_WED_WOIF_DISABLE_DONE,
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MTK_WED_WOIF_TRIGGER_ENABLE,
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MTK_WED_WOIF_ENABLE_DONE,
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MTK_WED_WOIF_TRIGGER_GATING,
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MTK_WED_WOIF_GATING_DONE,
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MTK_WED_WOIF_TRIGGER_HALT,
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MTK_WED_WOIF_HALT_DONE,
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};
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enum mtk_wed_dummy_cr_idx {
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MTK_WED_DUMMY_CR_FWDL,
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MTK_WED_DUMMY_CR_WO_STATUS,
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};
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#define MT7986_FIRMWARE_WO0 "mediatek/mt7986_wo_0.bin"
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#define MT7986_FIRMWARE_WO1 "mediatek/mt7986_wo_1.bin"
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#define MTK_WO_MCU_CFG_LS_BASE 0
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#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
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#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x004)
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#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x00c)
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#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x010)
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#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x014)
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#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x018)
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#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x01c)
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#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x050)
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#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x060)
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#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x064)
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#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK BIT(5)
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#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK BIT(0)
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#define MTK_WED_WO_RING_SIZE 256
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#define MTK_WED_WO_CMD_LEN 1504
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#define MTK_WED_WO_TXCH_NUM 0
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#define MTK_WED_WO_RXCH_NUM 1
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#define MTK_WED_WO_RXCH_WO_EXCEPTION 7
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#define MTK_WED_WO_TXCH_INT_MASK BIT(0)
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#define MTK_WED_WO_RXCH_INT_MASK BIT(1)
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#define MTK_WED_WO_EXCEPTION_INT_MASK BIT(7)
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#define MTK_WED_WO_ALL_INT_MASK (MTK_WED_WO_RXCH_INT_MASK | \
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MTK_WED_WO_EXCEPTION_INT_MASK)
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#define MTK_WED_WO_CCIF_BUSY 0x004
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#define MTK_WED_WO_CCIF_START 0x008
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#define MTK_WED_WO_CCIF_TCHNUM 0x00c
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#define MTK_WED_WO_CCIF_RCHNUM 0x010
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#define MTK_WED_WO_CCIF_RCHNUM_MASK GENMASK(7, 0)
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#define MTK_WED_WO_CCIF_ACK 0x014
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#define MTK_WED_WO_CCIF_IRQ0_MASK 0x018
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#define MTK_WED_WO_CCIF_IRQ1_MASK 0x01c
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#define MTK_WED_WO_CCIF_DUMMY1 0x020
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#define MTK_WED_WO_CCIF_DUMMY2 0x024
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#define MTK_WED_WO_CCIF_DUMMY3 0x028
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#define MTK_WED_WO_CCIF_DUMMY4 0x02c
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#define MTK_WED_WO_CCIF_SHADOW1 0x030
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#define MTK_WED_WO_CCIF_SHADOW2 0x034
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#define MTK_WED_WO_CCIF_SHADOW3 0x038
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#define MTK_WED_WO_CCIF_SHADOW4 0x03c
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#define MTK_WED_WO_CCIF_DUMMY5 0x050
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#define MTK_WED_WO_CCIF_DUMMY6 0x054
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#define MTK_WED_WO_CCIF_DUMMY7 0x058
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#define MTK_WED_WO_CCIF_DUMMY8 0x05c
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#define MTK_WED_WO_CCIF_SHADOW5 0x060
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#define MTK_WED_WO_CCIF_SHADOW6 0x064
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#define MTK_WED_WO_CCIF_SHADOW7 0x068
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#define MTK_WED_WO_CCIF_SHADOW8 0x06c
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#define MTK_WED_WO_CTL_SD_LEN1 GENMASK(13, 0)
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#define MTK_WED_WO_CTL_LAST_SEC1 BIT(14)
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#define MTK_WED_WO_CTL_BURST BIT(15)
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#define MTK_WED_WO_CTL_SD_LEN0_SHIFT 16
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#define MTK_WED_WO_CTL_SD_LEN0 GENMASK(29, 16)
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#define MTK_WED_WO_CTL_LAST_SEC0 BIT(30)
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#define MTK_WED_WO_CTL_DMA_DONE BIT(31)
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#define MTK_WED_WO_INFO_WINFO GENMASK(15, 0)
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struct mtk_wed_wo_memory_region {
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const char *name;
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void __iomem *addr;
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phys_addr_t phy_addr;
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u32 size;
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bool shared:1;
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bool consumed:1;
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};
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struct mtk_wed_fw_region {
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__le32 decomp_crc;
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__le32 decomp_len;
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__le32 decomp_blk_sz;
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u8 rsv0[4];
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__le32 addr;
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__le32 len;
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u8 feature_set;
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u8 rsv1[15];
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} __packed;
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struct mtk_wed_fw_trailer {
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u8 chip_id;
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u8 eco_code;
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u8 num_region;
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u8 format_ver;
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u8 format_flag;
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u8 rsv[2];
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char fw_ver[10];
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char build_date[15];
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u32 crc;
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};
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struct mtk_wed_wo_queue_regs {
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u32 desc_base;
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u32 ring_size;
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u32 cpu_idx;
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u32 dma_idx;
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};
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struct mtk_wed_wo_queue_desc {
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__le32 buf0;
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__le32 ctrl;
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__le32 buf1;
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__le32 info;
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__le32 reserved[4];
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} __packed __aligned(32);
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struct mtk_wed_wo_queue_entry {
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dma_addr_t addr;
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void *buf;
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u32 len;
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};
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struct mtk_wed_wo_queue {
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struct mtk_wed_wo_queue_regs regs;
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struct page_frag_cache cache;
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struct mtk_wed_wo_queue_desc *desc;
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dma_addr_t desc_dma;
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struct mtk_wed_wo_queue_entry *entry;
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u16 head;
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u16 tail;
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int n_desc;
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int queued;
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int buf_size;
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};
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struct mtk_wed_wo {
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struct mtk_wed_hw *hw;
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struct mtk_wed_wo_memory_region boot;
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struct mtk_wed_wo_queue q_tx;
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struct mtk_wed_wo_queue q_rx;
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struct {
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struct mutex mutex;
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int timeout;
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u16 seq;
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struct sk_buff_head res_q;
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wait_queue_head_t wait;
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} mcu;
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struct {
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struct regmap *regs;
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spinlock_t lock;
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struct tasklet_struct irq_tasklet;
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int irq;
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u32 irq_mask;
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} mmio;
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};
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static inline int
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mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
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{
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struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
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if (hdr->version)
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return -EINVAL;
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if (skb->len < sizeof(*hdr) || skb->len != le16_to_cpu(hdr->length))
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return -EINVAL;
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return 0;
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}
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void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
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void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
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struct sk_buff *skb);
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int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
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const void *data, int len, bool wait_resp);
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int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data,
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int len);
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int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
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int mtk_wed_wo_init(struct mtk_wed_hw *hw);
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void mtk_wed_wo_deinit(struct mtk_wed_hw *hw);
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int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *dev, struct mtk_wed_wo_queue *q,
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struct sk_buff *skb);
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#endif /* __MTK_WED_WO_H */
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