476 lines
13 KiB
C
476 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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This contains the functions to handle the enhanced descriptors.
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Copyright (C) 2007-2014 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/stmmac.h>
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#include "common.h"
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#include "descs_com.h"
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static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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unsigned int tdes0 = le32_to_cpu(p->des0);
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int ret = tx_done;
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/* Get tx owner first */
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if (unlikely(tdes0 & ETDES0_OWN))
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return tx_dma_own;
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/* Verify tx error by looking at the last segment. */
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if (likely(!(tdes0 & ETDES0_LAST_SEGMENT)))
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return tx_not_ls;
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if (unlikely(tdes0 & ETDES0_ERROR_SUMMARY)) {
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if (unlikely(tdes0 & ETDES0_JABBER_TIMEOUT))
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x->tx_jabber++;
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if (unlikely(tdes0 & ETDES0_FRAME_FLUSHED)) {
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x->tx_frame_flushed++;
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dwmac_dma_flush_tx_fifo(ioaddr);
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}
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if (unlikely(tdes0 & ETDES0_LOSS_CARRIER)) {
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(tdes0 & ETDES0_NO_CARRIER)) {
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely((tdes0 & ETDES0_LATE_COLLISION) ||
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(tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))
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stats->collisions +=
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(tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;
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if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))
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x->tx_deferred++;
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if (unlikely(tdes0 & ETDES0_UNDERFLOW_ERROR)) {
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dwmac_dma_flush_tx_fifo(ioaddr);
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x->tx_underflow++;
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}
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if (unlikely(tdes0 & ETDES0_IP_HEADER_ERROR))
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x->tx_ip_header_error++;
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if (unlikely(tdes0 & ETDES0_PAYLOAD_ERROR)) {
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x->tx_payload_error++;
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dwmac_dma_flush_tx_fifo(ioaddr);
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}
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ret = tx_err;
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}
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if (unlikely(tdes0 & ETDES0_DEFERRED))
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x->tx_deferred++;
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#ifdef STMMAC_VLAN_TAG_USED
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if (tdes0 & ETDES0_VLAN_FRAME)
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x->tx_vlan++;
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#endif
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return ret;
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}
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static int enh_desc_get_tx_len(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
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}
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static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
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{
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int ret = good_frame;
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u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
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/* bits 5 7 0 | Frame status
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* ----------------------------------------------------------
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* 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
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* 1 0 0 | IPv4/6 No CSUM errorS.
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* 1 0 1 | IPv4/6 CSUM PAYLOAD error
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* 1 1 0 | IPv4/6 CSUM IP HR error
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* 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
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* 0 0 1 | IPv4/6 unsupported IP PAYLOAD
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* 0 1 1 | COE bypassed.. no IPv4/6 frame
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* 0 1 0 | Reserved.
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*/
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if (status == 0x0)
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ret = llc_snap;
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else if (status == 0x4)
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ret = good_frame;
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else if (status == 0x5)
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ret = csum_none;
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else if (status == 0x6)
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ret = csum_none;
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else if (status == 0x7)
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ret = csum_none;
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else if (status == 0x1)
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ret = discard_frame;
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else if (status == 0x3)
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ret = discard_frame;
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return ret;
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}
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static void enh_desc_get_ext_status(void *data, struct stmmac_extra_stats *x,
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struct dma_extended_desc *p)
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{
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unsigned int rdes0 = le32_to_cpu(p->basic.des0);
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unsigned int rdes4 = le32_to_cpu(p->des4);
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if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {
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int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;
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if (rdes4 & ERDES4_IP_HDR_ERR)
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x->ip_hdr_err++;
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if (rdes4 & ERDES4_IP_PAYLOAD_ERR)
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x->ip_payload_err++;
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if (rdes4 & ERDES4_IP_CSUM_BYPASSED)
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x->ip_csum_bypassed++;
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if (rdes4 & ERDES4_IPV4_PKT_RCVD)
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x->ipv4_pkt_rcvd++;
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if (rdes4 & ERDES4_IPV6_PKT_RCVD)
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x->ipv6_pkt_rcvd++;
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if (message_type == RDES_EXT_NO_PTP)
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x->no_ptp_rx_msg_type_ext++;
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else if (message_type == RDES_EXT_SYNC)
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x->ptp_rx_msg_type_sync++;
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else if (message_type == RDES_EXT_FOLLOW_UP)
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x->ptp_rx_msg_type_follow_up++;
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else if (message_type == RDES_EXT_DELAY_REQ)
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x->ptp_rx_msg_type_delay_req++;
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else if (message_type == RDES_EXT_DELAY_RESP)
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x->ptp_rx_msg_type_delay_resp++;
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else if (message_type == RDES_EXT_PDELAY_REQ)
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x->ptp_rx_msg_type_pdelay_req++;
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else if (message_type == RDES_EXT_PDELAY_RESP)
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x->ptp_rx_msg_type_pdelay_resp++;
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else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
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x->ptp_rx_msg_type_pdelay_follow_up++;
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else if (message_type == RDES_PTP_ANNOUNCE)
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x->ptp_rx_msg_type_announce++;
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else if (message_type == RDES_PTP_MANAGEMENT)
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x->ptp_rx_msg_type_management++;
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else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
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x->ptp_rx_msg_pkt_reserved_type++;
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if (rdes4 & ERDES4_PTP_FRAME_TYPE)
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x->ptp_frame_type++;
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if (rdes4 & ERDES4_PTP_VER)
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x->ptp_ver++;
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if (rdes4 & ERDES4_TIMESTAMP_DROPPED)
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x->timestamp_dropped++;
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if (rdes4 & ERDES4_AV_PKT_RCVD)
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x->av_pkt_rcvd++;
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if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)
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x->av_tagged_pkt_rcvd++;
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if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)
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x->vlan_tag_priority_val++;
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if (rdes4 & ERDES4_L3_FILTER_MATCH)
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x->l3_filter_match++;
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if (rdes4 & ERDES4_L4_FILTER_MATCH)
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x->l4_filter_match++;
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if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)
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x->l3_l4_filter_no_match++;
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}
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}
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static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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unsigned int rdes0 = le32_to_cpu(p->des0);
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int ret = good_frame;
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if (unlikely(rdes0 & RDES0_OWN))
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return dma_own;
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if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {
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stats->rx_length_errors++;
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return discard_frame;
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}
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if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
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if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) {
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x->rx_desc++;
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stats->rx_length_errors++;
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}
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if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
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x->rx_gmac_overflow++;
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if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
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pr_err("\tIPC Csum Error/Giant frame\n");
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if (unlikely(rdes0 & RDES0_COLLISION))
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stats->collisions++;
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if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG))
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x->rx_watchdog++;
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if (unlikely(rdes0 & RDES0_MII_ERROR)) /* GMII */
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x->rx_mii++;
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if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
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x->rx_crc_errors++;
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stats->rx_crc_errors++;
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}
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ret = discard_frame;
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}
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/* After a payload csum error, the ES bit is set.
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* It doesn't match with the information reported into the databook.
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* At any rate, we need to understand if the CSUM hw computation is ok
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* and report this info to the upper layers. */
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if (likely(ret == good_frame))
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ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),
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!!(rdes0 & RDES0_FRAME_TYPE),
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!!(rdes0 & ERDES0_RX_MAC_ADDR));
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if (unlikely(rdes0 & RDES0_DRIBBLING))
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x->dribbling_bit++;
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if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL)) {
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x->sa_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(rdes0 & RDES0_DA_FILTER_FAIL)) {
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x->da_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
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x->rx_length++;
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ret = discard_frame;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (rdes0 & RDES0_VLAN_TAG)
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x->rx_vlan++;
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#endif
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return ret;
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}
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static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end, int bfsize)
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{
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int bfsize1;
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p->des0 |= cpu_to_le32(RDES0_OWN);
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bfsize1 = min(bfsize, BUF_SIZE_8KiB);
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p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);
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if (mode == STMMAC_CHAIN_MODE)
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ehn_desc_rx_set_on_chain(p);
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else
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ehn_desc_rx_set_on_ring(p, end, bfsize);
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if (disable_rx_ic)
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p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC);
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}
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static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)
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{
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p->des0 &= cpu_to_le32(~ETDES0_OWN);
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if (mode == STMMAC_CHAIN_MODE)
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enh_desc_end_tx_desc_on_chain(p);
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else
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enh_desc_end_tx_desc_on_ring(p, end);
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}
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static int enh_desc_get_tx_owner(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31;
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}
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static void enh_desc_set_tx_owner(struct dma_desc *p)
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{
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p->des0 |= cpu_to_le32(ETDES0_OWN);
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}
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static void enh_desc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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{
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p->des0 |= cpu_to_le32(RDES0_OWN);
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}
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static int enh_desc_get_tx_ls(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29;
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}
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static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
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{
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int ter = (le32_to_cpu(p->des0) & ETDES0_END_RING) >> 21;
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memset(p, 0, offsetof(struct dma_desc, des2));
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if (mode == STMMAC_CHAIN_MODE)
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enh_desc_end_tx_desc_on_chain(p);
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else
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enh_desc_end_tx_desc_on_ring(p, ter);
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}
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static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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bool csum_flag, int mode, bool tx_own,
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bool ls, unsigned int tot_pkt_len)
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{
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unsigned int tdes0 = le32_to_cpu(p->des0);
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if (mode == STMMAC_CHAIN_MODE)
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enh_set_tx_desc_len_on_chain(p, len);
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else
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enh_set_tx_desc_len_on_ring(p, len);
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if (is_fs)
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tdes0 |= ETDES0_FIRST_SEGMENT;
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else
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tdes0 &= ~ETDES0_FIRST_SEGMENT;
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if (likely(csum_flag))
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tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
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else
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tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
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if (ls)
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tdes0 |= ETDES0_LAST_SEGMENT;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes0 |= ETDES0_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des0 = cpu_to_le32(tdes0);
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}
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static void enh_desc_set_tx_ic(struct dma_desc *p)
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{
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p->des0 |= cpu_to_le32(ETDES0_INTERRUPT);
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}
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static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
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{
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unsigned int csum = 0;
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/* The type-1 checksum offload engines append the checksum at
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* the end of frame and the two bytes of checksum are added in
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* the length.
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* Adjust for that in the framelen for type-1 checksum offload
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* engines.
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*/
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if (rx_coe_type == STMMAC_RX_COE_TYPE1)
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csum = 2;
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return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
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>> RDES0_FRAME_LEN_SHIFT) - csum);
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}
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static void enh_desc_enable_tx_timestamp(struct dma_desc *p)
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{
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p->des0 |= cpu_to_le32(ETDES0_TIME_STAMP_ENABLE);
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}
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static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des0) & ETDES0_TIME_STAMP_STATUS) >> 17;
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}
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static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts)
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{
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u64 ns;
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if (ats) {
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struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
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ns = le32_to_cpu(p->des6);
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/* convert high/sec time stamp value to nanosecond */
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ns += le32_to_cpu(p->des7) * 1000000000ULL;
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} else {
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struct dma_desc *p = (struct dma_desc *)desc;
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ns = le32_to_cpu(p->des2);
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ns += le32_to_cpu(p->des3) * 1000000000ULL;
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}
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*ts = ns;
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}
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static int enh_desc_get_rx_timestamp_status(void *desc, void *next_desc,
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u32 ats)
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{
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if (ats) {
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struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
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return (le32_to_cpu(p->basic.des0) & RDES0_IPC_CSUM_ERROR) >> 7;
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} else {
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struct dma_desc *p = (struct dma_desc *)desc;
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if ((le32_to_cpu(p->des2) == 0xffffffff) &&
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(le32_to_cpu(p->des3) == 0xffffffff))
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/* timestamp is corrupted, hence don't store it */
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return 0;
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else
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return 1;
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}
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}
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static void enh_desc_display_ring(void *head, unsigned int size, bool rx,
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dma_addr_t dma_rx_phy, unsigned int desc_size)
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{
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struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
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dma_addr_t dma_addr;
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int i;
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pr_info("Extended %s descriptor ring:\n", rx ? "RX" : "TX");
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for (i = 0; i < size; i++) {
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u64 x;
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dma_addr = dma_rx_phy + i * sizeof(*ep);
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x = *(u64 *)ep;
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pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
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i, &dma_addr,
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(unsigned int)x, (unsigned int)(x >> 32),
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ep->basic.des2, ep->basic.des3);
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ep++;
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}
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pr_info("\n");
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}
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static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr)
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{
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p->des2 = cpu_to_le32(addr);
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}
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static void enh_desc_clear(struct dma_desc *p)
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{
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p->des2 = 0;
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}
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const struct stmmac_desc_ops enh_desc_ops = {
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.tx_status = enh_desc_get_tx_status,
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.rx_status = enh_desc_get_rx_status,
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.get_tx_len = enh_desc_get_tx_len,
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.init_rx_desc = enh_desc_init_rx_desc,
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.init_tx_desc = enh_desc_init_tx_desc,
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.get_tx_owner = enh_desc_get_tx_owner,
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.release_tx_desc = enh_desc_release_tx_desc,
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.prepare_tx_desc = enh_desc_prepare_tx_desc,
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.set_tx_ic = enh_desc_set_tx_ic,
|
|
.get_tx_ls = enh_desc_get_tx_ls,
|
|
.set_tx_owner = enh_desc_set_tx_owner,
|
|
.set_rx_owner = enh_desc_set_rx_owner,
|
|
.get_rx_frame_len = enh_desc_get_rx_frame_len,
|
|
.rx_extended_status = enh_desc_get_ext_status,
|
|
.enable_tx_timestamp = enh_desc_enable_tx_timestamp,
|
|
.get_tx_timestamp_status = enh_desc_get_tx_timestamp_status,
|
|
.get_timestamp = enh_desc_get_timestamp,
|
|
.get_rx_timestamp_status = enh_desc_get_rx_timestamp_status,
|
|
.display_ring = enh_desc_display_ring,
|
|
.set_addr = enh_desc_set_addr,
|
|
.clear = enh_desc_clear,
|
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};
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