146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "hal_desc.h"
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#include "hal.h"
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#include "hal_tx.h"
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#include "hif.h"
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#define DSCP_TID_MAP_TBL_ENTRY_SIZE 64
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/* dscp_tid_map - Default DSCP-TID mapping
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*=================
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* DSCP TID
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*=================
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* 000xxx 0
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* 001xxx 1
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* 010xxx 2
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* 011xxx 3
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* 100xxx 4
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* 101xxx 5
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* 110xxx 6
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* 111xxx 7
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*/
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static inline u8 dscp2tid(u8 dscp)
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{
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return dscp >> 3;
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}
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void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab,
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struct hal_tcl_data_cmd *tcl_cmd,
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struct hal_tx_info *ti)
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{
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tcl_cmd->buf_addr_info.info0 =
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le32_encode_bits(ti->paddr, BUFFER_ADDR_INFO0_ADDR);
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tcl_cmd->buf_addr_info.info1 =
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le32_encode_bits(((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT),
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BUFFER_ADDR_INFO1_ADDR);
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tcl_cmd->buf_addr_info.info1 |=
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le32_encode_bits((ti->rbm_id), BUFFER_ADDR_INFO1_RET_BUF_MGR) |
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le32_encode_bits(ti->desc_id, BUFFER_ADDR_INFO1_SW_COOKIE);
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tcl_cmd->info0 =
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le32_encode_bits(ti->type, HAL_TCL_DATA_CMD_INFO0_DESC_TYPE) |
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le32_encode_bits(ti->bank_id, HAL_TCL_DATA_CMD_INFO0_BANK_ID);
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tcl_cmd->info1 =
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le32_encode_bits(ti->meta_data_flags,
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HAL_TCL_DATA_CMD_INFO1_CMD_NUM);
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tcl_cmd->info2 = cpu_to_le32(ti->flags0) |
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le32_encode_bits(ti->data_len, HAL_TCL_DATA_CMD_INFO2_DATA_LEN) |
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le32_encode_bits(ti->pkt_offset, HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET);
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tcl_cmd->info3 = cpu_to_le32(ti->flags1) |
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le32_encode_bits(ti->tid, HAL_TCL_DATA_CMD_INFO3_TID) |
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le32_encode_bits(ti->lmac_id, HAL_TCL_DATA_CMD_INFO3_PMAC_ID) |
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le32_encode_bits(ti->vdev_id, HAL_TCL_DATA_CMD_INFO3_VDEV_ID);
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tcl_cmd->info4 = le32_encode_bits(ti->bss_ast_idx,
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HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX) |
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le32_encode_bits(ti->bss_ast_hash,
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HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM);
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tcl_cmd->info5 = 0;
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}
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void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id)
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{
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u32 ctrl_reg_val;
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u32 addr;
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u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE], dscp, tid;
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int i;
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u32 value;
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ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG);
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/* Enable read/write access */
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ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
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ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val);
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addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +
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(4 * id * (HAL_DSCP_TID_TBL_SIZE / 4));
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/* Configure each DSCP-TID mapping in three bits there by configure
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* three bytes in an iteration.
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*/
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for (i = 0, dscp = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 3) {
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tid = dscp2tid(dscp);
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value = u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP0);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP1);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP2);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP3);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP4);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP5);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP6);
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dscp++;
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tid = dscp2tid(dscp);
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value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP7);
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dscp++;
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memcpy(&hw_map_val[i], &value, 3);
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}
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for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) {
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ath12k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
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addr += 4;
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}
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/* Disable read/write access */
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ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG);
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ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
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ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
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HAL_TCL1_RING_CMN_CTRL_REG,
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ctrl_reg_val);
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}
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void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config,
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u8 bank_id)
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{
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ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id,
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bank_config);
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}
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