195 lines
5.9 KiB
C
195 lines
5.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef ATH12K_HAL_TX_H
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#define ATH12K_HAL_TX_H
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#include "hal_desc.h"
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#include "core.h"
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#define HAL_TX_ADDRX_EN 1
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#define HAL_TX_ADDRY_EN 2
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#define HAL_TX_ADDR_SEARCH_DEFAULT 0
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#define HAL_TX_ADDR_SEARCH_INDEX 1
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/* TODO: check all these data can be managed with struct ath12k_tx_desc_info for perf */
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struct hal_tx_info {
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u16 meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */
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u8 ring_id;
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u8 rbm_id;
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u32 desc_id;
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enum hal_tcl_desc_type type;
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enum hal_tcl_encap_type encap_type;
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dma_addr_t paddr;
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u32 data_len;
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u32 pkt_offset;
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enum hal_encrypt_type encrypt_type;
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u32 flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */
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u32 flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */
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u16 addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */
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u16 bss_ast_hash;
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u16 bss_ast_idx;
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u8 tid;
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u8 search_type; /* %HAL_TX_ADDR_SEARCH_ */
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u8 lmac_id;
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u8 vdev_id;
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u8 dscp_tid_tbl_idx;
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bool enable_mesh;
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int bank_id;
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};
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/* TODO: Check if the actual desc macros can be used instead */
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#define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0)
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#define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1)
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#define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2)
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#define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3)
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#define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4)
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#define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5)
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#define HAL_TX_STATUS_FLAGS_OFDMA BIT(6)
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#define HAL_TX_STATUS_DESC_LEN sizeof(struct hal_wbm_release_ring)
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/* Tx status parsed from srng desc */
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struct hal_tx_status {
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enum hal_wbm_rel_src_module buf_rel_source;
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enum hal_wbm_tqm_rel_reason status;
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u8 ack_rssi;
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u32 flags; /* %HAL_TX_STATUS_FLAGS_ */
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u32 ppdu_id;
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u8 try_cnt;
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u8 tid;
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u16 peer_id;
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u32 rate_stats;
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};
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#define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16)
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#define HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B BIT(20)
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#define HAL_TX_PHY_DESC_INFO0_PKT_TYPE GENMASK(24, 21)
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#define HAL_TX_PHY_DESC_INFO0_BANDWIDTH GENMASK(30, 28)
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#define HAL_TX_PHY_DESC_INFO1_MCS GENMASK(3, 0)
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#define HAL_TX_PHY_DESC_INFO1_STBC BIT(6)
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#define HAL_TX_PHY_DESC_INFO2_NSS GENMASK(23, 21)
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#define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW GENMASK(6, 4)
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#define HAL_TX_PHY_DESC_INFO3_LTF_SIZE GENMASK(20, 19)
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#define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL GENMASK(17, 15)
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struct hal_tx_phy_desc {
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__le32 info0;
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__le32 info1;
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__le32 info2;
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__le32 info3;
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} __packed;
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#define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0 GENMASK(15, 0)
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#define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16 GENMASK(31, 16)
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#define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0 GENMASK(15, 0)
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#define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16 GENMASK(31, 16)
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struct hal_tx_fes_status_prot {
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__le64 reserved;
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__le32 info0;
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__le32 info1;
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__le32 reserved1[11];
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} __packed;
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#define HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION GENMASK(15, 0)
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struct hal_tx_fes_status_user_ppdu {
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__le64 reserved;
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__le32 info0;
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__le32 reserved1[3];
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} __packed;
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#define HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32 GENMASK(31, 0)
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#define HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32 GENMASK(31, 0)
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struct hal_tx_fes_status_start_prot {
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__le32 info0;
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__le32 info1;
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__le64 reserved;
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} __packed;
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#define HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE GENMASK(29, 27)
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struct hal_tx_fes_status_start {
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__le32 reserved;
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__le32 info0;
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__le64 reserved1;
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} __packed;
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#define HAL_TX_Q_EXT_INFO0_FRAME_CTRL GENMASK(15, 0)
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#define HAL_TX_Q_EXT_INFO0_QOS_CTRL GENMASK(31, 16)
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#define HAL_TX_Q_EXT_INFO1_AMPDU_FLAG BIT(0)
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struct hal_tx_queue_exten {
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__le32 info0;
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__le32 info1;
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} __packed;
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#define HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS GENMASK(28, 23)
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struct hal_tx_fes_setup {
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__le32 schedule_id;
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__le32 info0;
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__le64 reserved;
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} __packed;
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#define HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE GENMASK(2, 0)
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#define HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0 GENMASK(31, 0)
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#define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32 GENMASK(15, 0)
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#define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0 GENMASK(31, 16)
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#define HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16 GENMASK(31, 0)
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#define HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0 GENMASK(31, 0)
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#define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32 GENMASK(15, 0)
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#define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0 GENMASK(31, 16)
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#define HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16 GENMASK(31, 0)
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struct hal_tx_pcu_ppdu_setup_init {
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__le32 info0;
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__le32 info1;
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__le32 info2;
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__le32 info3;
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__le32 reserved;
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__le32 info4;
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__le32 info5;
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__le32 info6;
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} __packed;
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#define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0 GENMASK(15, 0)
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#define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16 GENMASK(31, 16)
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struct hal_tx_fes_status_end {
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__le32 reserved[2];
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__le32 info0;
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__le32 reserved1[19];
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} __packed;
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#define HAL_TX_BANK_CONFIG_EPD BIT(0)
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#define HAL_TX_BANK_CONFIG_ENCAP_TYPE GENMASK(2, 1)
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#define HAL_TX_BANK_CONFIG_ENCRYPT_TYPE GENMASK(6, 3)
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#define HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP BIT(7)
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#define HAL_TX_BANK_CONFIG_LINK_META_SWAP BIT(8)
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#define HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN BIT(9)
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#define HAL_TX_BANK_CONFIG_ADDRX_EN BIT(10)
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#define HAL_TX_BANK_CONFIG_ADDRY_EN BIT(11)
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#define HAL_TX_BANK_CONFIG_MESH_EN GENMASK(13, 12)
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#define HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN BIT(14)
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#define HAL_TX_BANK_CONFIG_PMAC_ID GENMASK(16, 15)
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/* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */
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#define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID GENMASK(22, 17)
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void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab,
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struct hal_tcl_data_cmd *tcl_cmd,
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struct hal_tx_info *ti);
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void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id);
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int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng,
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enum hal_reo_cmd_type type,
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struct ath12k_hal_reo_cmd *cmd);
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void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config,
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u8 bank_id);
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#endif
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