557 lines
14 KiB
C
557 lines
14 KiB
C
// SPDX-License-Identifier: ISC
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include "mt76x02.h"
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#include "mt76x02_mcu.h"
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#include "trace.h"
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static void mt76x02_pre_tbtt_tasklet(struct tasklet_struct *t)
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{
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struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
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struct mt76_dev *mdev = &dev->mt76;
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struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];
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struct beacon_bc_data data = {};
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struct sk_buff *skb;
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int i;
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if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
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return;
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mt76x02_resync_beacon_timer(dev);
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/* Prevent corrupt transmissions during update */
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mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
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dev->beacon_data_count = 0;
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ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
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IEEE80211_IFACE_ITER_RESUME_ALL,
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mt76x02_update_beacon_iter, dev);
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mt76_wr(dev, MT_BCN_BYPASS_MASK,
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0xff00 | ~(0xff00 >> dev->beacon_data_count));
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mt76_csa_check(mdev);
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if (mdev->csa_complete)
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return;
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mt76x02_enqueue_buffered_bc(dev, &data, 8);
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if (!skb_queue_len(&data.q))
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return;
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for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
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if (!data.tail[i])
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continue;
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mt76_skb_set_moredata(data.tail[i], false);
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}
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spin_lock(&q->lock);
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while ((skb = __skb_dequeue(&data.q)) != NULL) {
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_vif *vif = info->control.vif;
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struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
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mt76_tx_queue_skb(dev, q, MT_TXQ_PSD, skb, &mvif->group_wcid,
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NULL);
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}
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spin_unlock(&q->lock);
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}
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static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
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{
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if (en)
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tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
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else
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tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
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}
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static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
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{
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mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
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if (en)
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mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
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else
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mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
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}
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void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
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{
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static const struct mt76x02_beacon_ops beacon_ops = {
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.nslots = 8,
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.slot_size = 1024,
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.pre_tbtt_enable = mt76x02e_pre_tbtt_enable,
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.beacon_enable = mt76x02e_beacon_enable,
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};
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dev->beacon_ops = &beacon_ops;
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/* Fire a pre-TBTT interrupt 8 ms before TBTT */
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mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
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8 << 4);
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mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
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MT_DFS_GP_INTERVAL);
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mt76_wr(dev, MT_INT_TIMER_EN, 0);
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mt76x02_init_beacon_config(dev);
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}
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EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config);
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static int
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mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
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int idx, int n_desc, int bufsize)
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{
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int err;
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err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
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MT_RX_RING_BASE);
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if (err < 0)
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return err;
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mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
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return 0;
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}
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static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
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{
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struct mt76x02_tx_status stat;
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u8 update = 1;
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while (kfifo_get(&dev->txstatus_fifo, &stat))
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mt76x02_send_tx_status(dev, &stat, &update);
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}
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static void mt76x02_tx_worker(struct mt76_worker *w)
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{
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struct mt76x02_dev *dev;
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dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);
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mt76x02_mac_poll_tx_status(dev, false);
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mt76x02_process_tx_status_fifo(dev);
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mt76_txq_schedule_all(&dev->mphy);
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}
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static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
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mt76.tx_napi);
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int i;
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mt76x02_mac_poll_tx_status(dev, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
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for (i = MT_TXQ_PSD; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
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if (napi_complete_done(napi, 0))
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mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
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for (i = MT_TXQ_PSD; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
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mt76_worker_schedule(&dev->mt76.tx_worker);
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return 0;
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}
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int mt76x02_dma_init(struct mt76x02_dev *dev)
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{
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struct mt76_txwi_cache __maybe_unused *t;
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int i, ret, fifo_size;
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struct mt76_queue *q;
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void *status_fifo;
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BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
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fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status));
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status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
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if (!status_fifo)
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return -ENOMEM;
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dev->mt76.tx_worker.fn = mt76x02_tx_worker;
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tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);
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spin_lock_init(&dev->txstatus_fifo_lock);
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kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
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mt76_dma_attach(&dev->mt76);
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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for (i = 0; i < IEEE80211_NUM_ACS; i++) {
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ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
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MT76x02_TX_RING_SIZE,
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MT_TX_RING_BASE, 0);
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if (ret)
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return ret;
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}
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ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
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MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE, 0);
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if (ret)
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return ret;
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
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MT_MCU_RING_SIZE, MT_TX_RING_BASE);
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if (ret)
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return ret;
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mt76x02_irq_enable(dev,
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MT_INT_TX_DONE(IEEE80211_AC_VO) |
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MT_INT_TX_DONE(IEEE80211_AC_VI) |
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MT_INT_TX_DONE(IEEE80211_AC_BE) |
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MT_INT_TX_DONE(IEEE80211_AC_BK) |
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MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) |
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MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU));
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ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
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MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
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if (ret)
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return ret;
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q = &dev->mt76.q_rx[MT_RXQ_MAIN];
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q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
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ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
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MT_RX_BUF_SIZE);
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if (ret)
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return ret;
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ret = mt76_init_queues(dev, mt76_dma_rx_poll);
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if (ret)
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return ret;
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netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
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mt76x02_poll_tx);
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napi_enable(&dev->mt76.tx_napi);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt76x02_dma_init);
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void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
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{
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struct mt76x02_dev *dev;
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dev = container_of(mdev, struct mt76x02_dev, mt76);
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mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
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}
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EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
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irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
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{
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struct mt76x02_dev *dev = dev_instance;
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u32 intr, mask;
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intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
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intr &= dev->mt76.mmio.irqmask;
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mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
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if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
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return IRQ_NONE;
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trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
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mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER);
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if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT))
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mask |= MT_INT_TX_DONE_ALL;
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mt76x02_irq_disable(dev, mask);
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if (intr & MT_INT_RX_DONE(0))
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napi_schedule(&dev->mt76.napi[0]);
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if (intr & MT_INT_RX_DONE(1))
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napi_schedule(&dev->mt76.napi[1]);
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if (intr & MT_INT_PRE_TBTT)
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tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
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/* send buffered multicast frames now */
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if (intr & MT_INT_TBTT) {
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if (dev->mt76.csa_complete)
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mt76_csa_finish(&dev->mt76);
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else
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mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);
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}
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if (intr & MT_INT_TX_STAT)
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mt76x02_mac_poll_tx_status(dev, true);
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if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL))
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napi_schedule(&dev->mt76.tx_napi);
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if (intr & MT_INT_GPTIMER)
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tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(mt76x02_irq_handler);
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static void mt76x02_dma_enable(struct mt76x02_dev *dev)
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{
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u32 val;
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mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
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mt76x02_wait_for_wpdma(&dev->mt76, 1000);
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usleep_range(50, 100);
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val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
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MT_WPDMA_GLO_CFG_TX_DMA_EN |
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MT_WPDMA_GLO_CFG_RX_DMA_EN;
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mt76_set(dev, MT_WPDMA_GLO_CFG, val);
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mt76_clear(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
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}
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void mt76x02_dma_disable(struct mt76x02_dev *dev)
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{
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u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
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val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
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MT_WPDMA_GLO_CFG_BIG_ENDIAN |
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MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
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val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
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mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
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}
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EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
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void mt76x02_mac_start(struct mt76x02_dev *dev)
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{
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mt76x02_mac_reset_counters(dev);
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mt76x02_dma_enable(dev);
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mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
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mt76_wr(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_ENABLE_TX |
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MT_MAC_SYS_CTRL_ENABLE_RX);
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mt76x02_irq_enable(dev,
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MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
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MT_INT_TX_STAT);
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}
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EXPORT_SYMBOL_GPL(mt76x02_mac_start);
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static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
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{
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u32 dma_idx, prev_dma_idx;
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struct mt76_queue *q;
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int i;
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for (i = 0; i < 4; i++) {
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q = dev->mphy.q_tx[i];
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prev_dma_idx = dev->mt76.tx_dma_idx[i];
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dma_idx = readl(&q->regs->dma_idx);
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dev->mt76.tx_dma_idx[i] = dma_idx;
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if (!q->queued || prev_dma_idx != dma_idx) {
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dev->tx_hang_check[i] = 0;
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continue;
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}
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if (++dev->tx_hang_check[i] >= MT_TX_HANG_TH)
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return true;
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}
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return false;
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}
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static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key, void *data)
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{
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struct mt76x02_dev *dev = hw->priv;
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struct mt76_wcid *wcid;
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if (!sta)
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return;
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wcid = (struct mt76_wcid *)sta->drv_priv;
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if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
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return;
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mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
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}
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static void mt76x02_reset_state(struct mt76x02_dev *dev)
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{
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int i;
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lockdep_assert_held(&dev->mt76.mutex);
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clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
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rcu_read_lock();
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ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
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rcu_read_unlock();
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for (i = 0; i < MT76x02_N_WCIDS; i++) {
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struct ieee80211_sta *sta;
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struct ieee80211_vif *vif;
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struct mt76x02_sta *msta;
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struct mt76_wcid *wcid;
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void *priv;
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wcid = rcu_dereference_protected(dev->mt76.wcid[i],
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lockdep_is_held(&dev->mt76.mutex));
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if (!wcid)
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continue;
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rcu_assign_pointer(dev->mt76.wcid[i], NULL);
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priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
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sta = container_of(priv, struct ieee80211_sta, drv_priv);
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priv = msta->vif;
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vif = container_of(priv, struct ieee80211_vif, drv_priv);
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__mt76_sta_remove(&dev->mt76, vif, sta);
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memset(msta, 0, sizeof(*msta));
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}
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dev->mt76.vif_mask = 0;
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dev->mt76.beacon_mask = 0;
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}
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static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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{
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u32 mask = dev->mt76.mmio.irqmask;
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bool restart = dev->mt76.mcu_ops->mcu_restart;
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int i;
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ieee80211_stop_queues(dev->mt76.hw);
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set_bit(MT76_RESET, &dev->mphy.state);
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tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
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mt76_worker_disable(&dev->mt76.tx_worker);
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napi_disable(&dev->mt76.tx_napi);
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mt76_for_each_q_rx(&dev->mt76, i) {
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napi_disable(&dev->mt76.napi[i]);
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}
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mutex_lock(&dev->mt76.mutex);
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dev->mcu_timeout = 0;
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if (restart)
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mt76x02_reset_state(dev);
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if (dev->mt76.beacon_mask)
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mt76_clear(dev, MT_BEACON_TIME_CFG,
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MT_BEACON_TIME_CFG_BEACON_TX |
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MT_BEACON_TIME_CFG_TBTT_EN);
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mt76x02_irq_disable(dev, mask);
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/* perform device reset */
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mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
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mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
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mt76_clear(dev, MT_WPDMA_GLO_CFG,
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|
MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
|
|
usleep_range(5000, 10000);
|
|
mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
|
|
|
|
/* let fw reset DMA */
|
|
mt76_set(dev, 0x734, 0x3);
|
|
|
|
if (restart)
|
|
mt76_mcu_restart(dev);
|
|
|
|
mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
|
|
for (i = 0; i < __MT_TXQ_MAX; i++)
|
|
mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
|
|
|
|
mt76_for_each_q_rx(&dev->mt76, i) {
|
|
mt76_queue_rx_reset(dev, i);
|
|
}
|
|
|
|
mt76_tx_status_check(&dev->mt76, true);
|
|
|
|
mt76x02_mac_start(dev);
|
|
|
|
if (dev->ed_monitor)
|
|
mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
|
|
|
|
if (dev->mt76.beacon_mask && !restart)
|
|
mt76_set(dev, MT_BEACON_TIME_CFG,
|
|
MT_BEACON_TIME_CFG_BEACON_TX |
|
|
MT_BEACON_TIME_CFG_TBTT_EN);
|
|
|
|
mt76x02_irq_enable(dev, mask);
|
|
|
|
mutex_unlock(&dev->mt76.mutex);
|
|
|
|
clear_bit(MT76_RESET, &dev->mphy.state);
|
|
|
|
mt76_worker_enable(&dev->mt76.tx_worker);
|
|
tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
|
|
|
|
local_bh_disable();
|
|
napi_enable(&dev->mt76.tx_napi);
|
|
napi_schedule(&dev->mt76.tx_napi);
|
|
|
|
mt76_for_each_q_rx(&dev->mt76, i) {
|
|
napi_enable(&dev->mt76.napi[i]);
|
|
napi_schedule(&dev->mt76.napi[i]);
|
|
}
|
|
local_bh_enable();
|
|
|
|
if (restart) {
|
|
set_bit(MT76_RESTART, &dev->mphy.state);
|
|
mt76x02_mcu_function_select(dev, Q_SELECT, 1);
|
|
ieee80211_restart_hw(dev->mt76.hw);
|
|
} else {
|
|
ieee80211_wake_queues(dev->mt76.hw);
|
|
mt76_txq_schedule_all(&dev->mphy);
|
|
}
|
|
}
|
|
|
|
void mt76x02_reconfig_complete(struct ieee80211_hw *hw,
|
|
enum ieee80211_reconfig_type reconfig_type)
|
|
{
|
|
struct mt76x02_dev *dev = hw->priv;
|
|
|
|
if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART)
|
|
return;
|
|
|
|
clear_bit(MT76_RESTART, &dev->mphy.state);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete);
|
|
|
|
static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
|
|
{
|
|
if (test_bit(MT76_RESTART, &dev->mphy.state))
|
|
return;
|
|
|
|
if (!mt76x02_tx_hang(dev) && !dev->mcu_timeout)
|
|
return;
|
|
|
|
mt76x02_watchdog_reset(dev);
|
|
|
|
dev->tx_hang_reset++;
|
|
memset(dev->tx_hang_check, 0, sizeof(dev->tx_hang_check));
|
|
memset(dev->mt76.tx_dma_idx, 0xff,
|
|
sizeof(dev->mt76.tx_dma_idx));
|
|
}
|
|
|
|
void mt76x02_wdt_work(struct work_struct *work)
|
|
{
|
|
struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
|
|
wdt_work.work);
|
|
|
|
mt76x02_check_tx_hang(dev);
|
|
|
|
ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,
|
|
MT_WATCHDOG_TIME);
|
|
}
|