239 lines
7.1 KiB
C
239 lines
7.1 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2012 Intel Corporation. All rights reserved.
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* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel PCIe NTB Linux driver
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*/
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#ifndef NTB_HW_INTEL_H
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#define NTB_HW_INTEL_H
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#include <linux/ntb.h>
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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/* PCI device IDs */
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
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#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
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#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
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/* Ntb control and link status */
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#define NTB_CTL_CFG_LOCK BIT(0)
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#define NTB_CTL_DISABLE BIT(1)
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#define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
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#define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
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#define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
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#define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
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#define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
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#define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
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#define NTB_LNK_STA_ACTIVE_BIT 0x2000
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#define NTB_LNK_STA_SPEED_MASK 0x000f
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#define NTB_LNK_STA_WIDTH_MASK 0x03f0
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#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
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#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
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/* flags to indicate unsafe api */
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#define NTB_UNSAFE_DB BIT_ULL(0)
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#define NTB_UNSAFE_SPAD BIT_ULL(1)
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#define NTB_BAR_MASK_64 ~(0xfull)
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#define NTB_BAR_MASK_32 ~(0xfu)
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struct intel_ntb_dev;
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struct intel_ntb_reg {
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int (*poll_link)(struct intel_ntb_dev *ndev);
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int (*link_is_up)(struct intel_ntb_dev *ndev);
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u64 (*db_ioread)(const void __iomem *mmio);
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void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
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unsigned long ntb_ctl;
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resource_size_t db_size;
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int mw_bar[];
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};
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struct intel_ntb_alt_reg {
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unsigned long db_bell;
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unsigned long db_mask;
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unsigned long db_clear;
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unsigned long spad;
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};
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struct intel_ntb_xlat_reg {
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unsigned long bar0_base;
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unsigned long bar2_xlat;
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unsigned long bar2_limit;
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unsigned short bar2_idx;
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};
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struct intel_b2b_addr {
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phys_addr_t bar0_addr;
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phys_addr_t bar2_addr64;
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phys_addr_t bar4_addr64;
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phys_addr_t bar4_addr32;
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phys_addr_t bar5_addr32;
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};
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struct intel_ntb_vec {
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struct intel_ntb_dev *ndev;
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int num;
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};
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struct intel_ntb_dev {
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struct ntb_dev ntb;
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/* offset of peer bar0 in b2b bar */
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unsigned long b2b_off;
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/* mw idx used to access peer bar0 */
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unsigned int b2b_idx;
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/* BAR45 is split into BAR4 and BAR5 */
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bool bar4_split;
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u32 ntb_ctl;
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u32 lnk_sta;
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unsigned char mw_count;
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unsigned char spad_count;
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unsigned char db_count;
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unsigned char db_vec_count;
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unsigned char db_vec_shift;
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u64 db_valid_mask;
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u64 db_link_mask;
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u64 db_mask;
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/* synchronize rmw access of db_mask and hw reg */
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spinlock_t db_mask_lock;
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struct msix_entry *msix;
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struct intel_ntb_vec *vec;
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const struct intel_ntb_reg *reg;
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const struct intel_ntb_alt_reg *self_reg;
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const struct intel_ntb_alt_reg *peer_reg;
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const struct intel_ntb_xlat_reg *xlat_reg;
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void __iomem *self_mmio;
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void __iomem *peer_mmio;
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phys_addr_t peer_addr;
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unsigned long last_ts;
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struct delayed_work hb_timer;
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unsigned long hwerr_flags;
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unsigned long unsafe_flags;
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unsigned long unsafe_flags_ignore;
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struct dentry *debugfs_dir;
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struct dentry *debugfs_info;
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/* gen4 entries */
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int dev_up;
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};
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#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
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#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
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hb_timer.work)
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static inline int pdev_is_gen1(struct pci_dev *pdev)
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{
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
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case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
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case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
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case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
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case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
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case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
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case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
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case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
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case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
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case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
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case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
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case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
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case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
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case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
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case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
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return 1;
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}
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return 0;
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}
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static inline int pdev_is_gen3(struct pci_dev *pdev)
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{
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if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
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return 1;
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return 0;
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}
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static inline int pdev_is_gen4(struct pci_dev *pdev)
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{
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if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
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return 1;
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return 0;
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}
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static inline int pdev_is_gen5(struct pci_dev *pdev)
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{
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return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
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}
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#endif
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