296 lines
7.1 KiB
C
296 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32 Factory-programmed memory read access driver
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*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of_device.h>
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#include <linux/tee_drv.h>
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#include "stm32-bsec-optee-ta.h"
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/* BSEC secure service access from non-secure */
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#define STM32_SMC_BSEC 0x82001003
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#define STM32_SMC_READ_SHADOW 0x01
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#define STM32_SMC_PROG_OTP 0x02
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#define STM32_SMC_WRITE_SHADOW 0x03
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#define STM32_SMC_READ_OTP 0x04
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/* shadow registers offset */
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#define STM32MP15_BSEC_DATA0 0x200
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struct stm32_romem_cfg {
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int size;
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u8 lower;
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bool ta;
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};
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struct stm32_romem_priv {
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void __iomem *base;
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struct nvmem_config cfg;
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u8 lower;
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struct tee_context *ctx;
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};
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static int stm32_romem_read(void *context, unsigned int offset, void *buf,
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size_t bytes)
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{
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struct stm32_romem_priv *priv = context;
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u8 *buf8 = buf;
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int i;
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for (i = offset; i < offset + bytes; i++)
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*buf8++ = readb_relaxed(priv->base + i);
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return 0;
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}
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static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
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{
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#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
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struct arm_smccc_res res;
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arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
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if (res.a0)
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return -EIO;
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if (result)
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*result = (u32)res.a1;
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return 0;
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#else
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return -ENXIO;
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#endif
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}
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static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
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size_t bytes)
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{
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struct stm32_romem_priv *priv = context;
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struct device *dev = priv->cfg.dev;
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u32 roffset, rbytes, val;
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u8 *buf8 = buf, *val8 = (u8 *)&val;
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int i, j = 0, ret, skip_bytes, size;
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/* Round unaligned access to 32-bits */
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roffset = rounddown(offset, 4);
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skip_bytes = offset & 0x3;
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rbytes = roundup(bytes + skip_bytes, 4);
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if (roffset + rbytes > priv->cfg.size)
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return -EINVAL;
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for (i = roffset; (i < roffset + rbytes); i += 4) {
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u32 otp = i >> 2;
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if (otp < priv->lower) {
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/* read lower data from shadow registers */
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val = readl_relaxed(
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priv->base + STM32MP15_BSEC_DATA0 + i);
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} else {
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ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
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&val);
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if (ret) {
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dev_err(dev, "Can't read data%d (%d)\n", otp,
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ret);
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return ret;
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}
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}
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/* skip first bytes in case of unaligned read */
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if (skip_bytes)
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size = min(bytes, (size_t)(4 - skip_bytes));
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else
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size = min(bytes, (size_t)4);
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memcpy(&buf8[j], &val8[skip_bytes], size);
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bytes -= size;
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j += size;
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skip_bytes = 0;
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}
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return 0;
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}
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static int stm32_bsec_write(void *context, unsigned int offset, void *buf,
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size_t bytes)
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{
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struct stm32_romem_priv *priv = context;
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struct device *dev = priv->cfg.dev;
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u32 *buf32 = buf;
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int ret, i;
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/* Allow only writing complete 32-bits aligned words */
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if ((bytes % 4) || (offset % 4))
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return -EINVAL;
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for (i = offset; i < offset + bytes; i += 4) {
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ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
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NULL);
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if (ret) {
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dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
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return ret;
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}
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}
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if (offset + bytes >= priv->lower * 4)
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dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n");
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return 0;
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}
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static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf,
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size_t bytes)
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{
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struct stm32_romem_priv *priv = context;
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return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);
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}
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static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf,
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size_t bytes)
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{
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struct stm32_romem_priv *priv = context;
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return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);
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}
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static bool stm32_bsec_smc_check(void)
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{
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u32 val;
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int ret;
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/* check that the OP-TEE support the BSEC SMC (legacy mode) */
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ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);
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return !ret;
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}
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static bool optee_presence_check(void)
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{
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struct device_node *np;
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bool tee_detected = false;
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/* check that the OP-TEE node is present and available. */
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np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
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if (np && of_device_is_available(np))
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tee_detected = true;
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of_node_put(np);
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return tee_detected;
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}
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static int stm32_romem_probe(struct platform_device *pdev)
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{
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const struct stm32_romem_cfg *cfg;
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struct device *dev = &pdev->dev;
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struct stm32_romem_priv *priv;
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struct resource *res;
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int rc;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->cfg.name = "stm32-romem";
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priv->cfg.word_size = 1;
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priv->cfg.stride = 1;
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priv->cfg.dev = dev;
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priv->cfg.priv = priv;
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priv->cfg.owner = THIS_MODULE;
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priv->cfg.type = NVMEM_TYPE_OTP;
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priv->lower = 0;
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cfg = (const struct stm32_romem_cfg *)
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of_match_device(dev->driver->of_match_table, dev)->data;
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if (!cfg) {
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priv->cfg.read_only = true;
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priv->cfg.size = resource_size(res);
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priv->cfg.reg_read = stm32_romem_read;
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} else {
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priv->cfg.size = cfg->size;
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priv->lower = cfg->lower;
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if (cfg->ta || optee_presence_check()) {
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rc = stm32_bsec_optee_ta_open(&priv->ctx);
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if (rc) {
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/* wait for OP-TEE client driver to be up and ready */
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if (rc == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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/* BSEC PTA is required or SMC not supported */
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if (cfg->ta || !stm32_bsec_smc_check())
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return rc;
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}
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}
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if (priv->ctx) {
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rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);
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if (rc) {
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dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);
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return rc;
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}
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priv->cfg.reg_read = stm32_bsec_pta_read;
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priv->cfg.reg_write = stm32_bsec_pta_write;
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} else {
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priv->cfg.reg_read = stm32_bsec_read;
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priv->cfg.reg_write = stm32_bsec_write;
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}
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}
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return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
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}
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/*
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* STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
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* => 96 x 32-bits data words
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* - Lower: 1K bits, 2:1 redundancy, incremental bit programming
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* => 32 (x 32-bits) lower shadow registers = words 0 to 31
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* - Upper: 2K bits, ECC protection, word programming only
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* => 64 (x 32-bits) = words 32 to 95
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*/
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static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
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.size = 384,
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.lower = 32,
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.ta = false,
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};
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static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {
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.size = 384,
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.lower = 32,
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.ta = true,
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};
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static const struct of_device_id stm32_romem_of_match[] = {
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{ .compatible = "st,stm32f4-otp", }, {
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.compatible = "st,stm32mp15-bsec",
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.data = (void *)&stm32mp15_bsec_cfg,
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}, {
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.compatible = "st,stm32mp13-bsec",
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.data = (void *)&stm32mp13_bsec_cfg,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
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static struct platform_driver stm32_romem_driver = {
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.probe = stm32_romem_probe,
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.driver = {
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.name = "stm32-romem",
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.of_match_table = of_match_ptr(stm32_romem_of_match),
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},
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};
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module_platform_driver(stm32_romem_driver);
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MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
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MODULE_ALIAS("platform:nvmem-stm32-romem");
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MODULE_LICENSE("GPL v2");
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