807 lines
20 KiB
C
807 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// S3C64xx specific support for pinctrl-samsung driver.
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//
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// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
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//
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// Based on pinctrl-exynos.c, please see the file for original copyrights.
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//
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// This file contains the Samsung S3C64xx specific information required by the
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// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
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// external gpio and wakeup interrupt support.
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "pinctrl-samsung.h"
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#define NUM_EINT0 28
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#define NUM_EINT0_IRQ 4
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#define EINT_MAX_PER_REG 16
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#define EINT_MAX_PER_GROUP 16
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/* External GPIO and wakeup interrupt related definitions */
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#define SVC_GROUP_SHIFT 4
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#define SVC_GROUP_MASK 0xf
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#define SVC_NUM_MASK 0xf
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#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
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SVC_GROUP_MASK)
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#define EINT12CON_REG 0x200
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#define EINT12MASK_REG 0x240
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#define EINT12PEND_REG 0x260
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#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
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#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
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#define EINT_REG(g) (4 * ((g) / 2))
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#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
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#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
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#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
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#define SERVICE_REG 0x284
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#define SERVICEPEND_REG 0x288
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#define EINT0CON0_REG 0x900
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#define EINT0MASK_REG 0x920
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#define EINT0PEND_REG 0x924
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/* S3C64xx specific external interrupt trigger types */
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#define EINT_LEVEL_LOW 0
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#define EINT_LEVEL_HIGH 1
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#define EINT_EDGE_FALLING 2
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#define EINT_EDGE_RISING 4
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#define EINT_EDGE_BOTH 6
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#define EINT_CON_MASK 0xF
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#define EINT_CON_LEN 4
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static const struct samsung_pin_bank_type bank_type_4bit_off = {
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.fld_width = { 4, 1, 2, 0, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
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};
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static const struct samsung_pin_bank_type bank_type_4bit_alive = {
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.fld_width = { 4, 1, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, },
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};
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static const struct samsung_pin_bank_type bank_type_4bit2_off = {
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.fld_width = { 4, 1, 2, 0, 2, 2, },
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.reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
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};
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static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
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.fld_width = { 4, 1, 2, },
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.reg_offset = { 0x00, 0x08, 0x0c, },
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};
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static const struct samsung_pin_bank_type bank_type_2bit_off = {
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.fld_width = { 2, 1, 2, 0, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
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};
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static const struct samsung_pin_bank_type bank_type_2bit_alive = {
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.fld_width = { 2, 1, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, },
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};
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#define PIN_BANK_4BIT(pins, reg, id) \
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{ \
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.type = &bank_type_4bit_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
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{ \
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.type = &bank_type_4bit_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_func = 7, \
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.eint_mask = (1 << (pins)) - 1, \
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.eint_offset = eoffs, \
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.name = id \
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}
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#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
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{ \
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.type = &bank_type_4bit_alive,\
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_func = 3, \
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.eint_mask = emask, \
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.eint_offset = eoffs, \
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.name = id \
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}
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#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
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{ \
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.type = &bank_type_4bit2_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_func = 7, \
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.eint_mask = (1 << (pins)) - 1, \
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.eint_offset = eoffs, \
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.name = id \
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}
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#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
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{ \
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.type = &bank_type_4bit2_alive,\
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_func = 3, \
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.eint_mask = emask, \
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.eint_offset = eoffs, \
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.name = id \
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}
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#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
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{ \
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.type = &bank_type_4bit2_alive,\
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define PIN_BANK_2BIT(pins, reg, id) \
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{ \
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.type = &bank_type_2bit_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
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{ \
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.type = &bank_type_2bit_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_func = 3, \
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.eint_mask = emask, \
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.eint_offset = eoffs, \
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.name = id \
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}
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#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
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{ \
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.type = &bank_type_2bit_alive,\
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_func = 2, \
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.eint_mask = (1 << (pins)) - 1, \
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.eint_offset = eoffs, \
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.name = id \
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}
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/**
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* struct s3c64xx_eint0_data - EINT0 common data
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* @drvdata: pin controller driver data
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* @domains: IRQ domains of particular EINT0 interrupts
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* @pins: pin offsets inside of banks of particular EINT0 interrupts
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*/
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struct s3c64xx_eint0_data {
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struct samsung_pinctrl_drv_data *drvdata;
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struct irq_domain *domains[NUM_EINT0];
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u8 pins[NUM_EINT0];
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};
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/**
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* struct s3c64xx_eint0_domain_data - EINT0 per-domain data
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* @bank: pin bank related to the domain
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* @eints: EINT0 interrupts related to the domain
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*/
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struct s3c64xx_eint0_domain_data {
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struct samsung_pin_bank *bank;
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u8 eints[];
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};
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/**
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* struct s3c64xx_eint_gpio_data - GPIO EINT data
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* @drvdata: pin controller driver data
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* @domains: array of domains related to EINT interrupt groups
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*/
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struct s3c64xx_eint_gpio_data {
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struct samsung_pinctrl_drv_data *drvdata;
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struct irq_domain *domains[];
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};
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/*
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* Common functions for S3C64xx EINT configuration
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*/
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static int s3c64xx_irq_get_trigger(unsigned int type)
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{
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int trigger;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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trigger = EINT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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trigger = EINT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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trigger = EINT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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trigger = EINT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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trigger = EINT_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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return trigger;
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}
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static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
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{
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/* Edge- and level-triggered interrupts need different handlers */
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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}
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static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
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struct samsung_pin_bank *bank, int pin)
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{
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const struct samsung_pin_bank_type *bank_type = bank->type;
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unsigned long flags;
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void __iomem *reg;
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u8 shift;
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u32 mask;
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u32 val;
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/* Make sure that pin is configured as interrupt */
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reg = d->virt_base + bank->pctl_offset;
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shift = pin;
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if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
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/* 4-bit bank type with 2 con regs */
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reg += 4;
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shift -= 8;
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}
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shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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raw_spin_lock_irqsave(&bank->slock, flags);
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val = readl(reg);
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val &= ~(mask << shift);
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val |= bank->eint_func << shift;
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writel(val, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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/*
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* Functions for EINT GPIO configuration (EINT groups 1-9)
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*/
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static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
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void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
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u32 val;
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val = readl(reg);
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if (mask)
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val |= 1 << index;
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else
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val &= ~(1 << index);
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writel(val, reg);
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}
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static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
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{
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s3c64xx_gpio_irq_set_mask(irqd, false);
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}
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static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
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{
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s3c64xx_gpio_irq_set_mask(irqd, true);
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}
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static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
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void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
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writel(1 << index, reg);
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}
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static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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void __iomem *reg;
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int trigger;
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u8 shift;
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u32 val;
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trigger = s3c64xx_irq_get_trigger(type);
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if (trigger < 0) {
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pr_err("unsupported external interrupt type\n");
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return -EINVAL;
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}
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s3c64xx_irq_set_handler(irqd, type);
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/* Set up interrupt trigger */
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reg = d->virt_base + EINTCON_REG(bank->eint_offset);
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shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
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shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
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val = readl(reg);
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val &= ~(EINT_CON_MASK << shift);
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val |= trigger << shift;
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writel(val, reg);
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s3c64xx_irq_set_function(d, bank, irqd->hwirq);
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return 0;
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}
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/*
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* irq_chip for gpio interrupts.
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*/
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static struct irq_chip s3c64xx_gpio_irq_chip = {
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.name = "GPIO",
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.irq_unmask = s3c64xx_gpio_irq_unmask,
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.irq_mask = s3c64xx_gpio_irq_mask,
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.irq_ack = s3c64xx_gpio_irq_ack,
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.irq_set_type = s3c64xx_gpio_irq_set_type,
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};
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static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct samsung_pin_bank *bank = h->host_data;
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if (!(bank->eint_mask & (1 << hw)))
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return -EINVAL;
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irq_set_chip_and_handler(virq,
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&s3c64xx_gpio_irq_chip, handle_level_irq);
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irq_set_chip_data(virq, bank);
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return 0;
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}
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/*
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* irq domain callbacks for external gpio interrupt controller.
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*/
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static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
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.map = s3c64xx_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
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struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
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chained_irq_enter(chip, desc);
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do {
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unsigned int svc;
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unsigned int group;
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unsigned int pin;
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int ret;
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svc = readl(drvdata->virt_base + SERVICE_REG);
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group = SVC_GROUP(svc);
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pin = svc & SVC_NUM_MASK;
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if (!group)
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break;
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/* Group 1 is used for two pin banks */
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if (group == 1) {
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if (pin < 8)
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group = 0;
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else
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pin -= 8;
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}
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ret = generic_handle_domain_irq(data->domains[group], pin);
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/*
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* Something must be really wrong if an unmapped EINT
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* was unmasked...
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*/
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BUG_ON(ret);
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} while (1);
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chained_irq_exit(chip, desc);
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}
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/**
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* s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
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* @d: driver data of samsung pinctrl driver.
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*/
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static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
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{
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struct s3c64xx_eint_gpio_data *data;
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struct samsung_pin_bank *bank;
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struct device *dev = d->dev;
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unsigned int nr_domains;
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unsigned int i;
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if (!d->irq) {
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dev_err(dev, "irq number not available\n");
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return -EINVAL;
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}
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nr_domains = 0;
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bank = d->pin_banks;
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for (i = 0; i < d->nr_banks; ++i, ++bank) {
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unsigned int nr_eints;
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unsigned int mask;
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if (bank->eint_type != EINT_TYPE_GPIO)
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continue;
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mask = bank->eint_mask;
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nr_eints = fls(mask);
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bank->irq_domain = irq_domain_create_linear(bank->fwnode,
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nr_eints, &s3c64xx_gpio_irqd_ops, bank);
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if (!bank->irq_domain) {
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dev_err(dev, "gpio irq domain add failed\n");
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return -ENXIO;
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}
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++nr_domains;
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}
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data = devm_kzalloc(dev, struct_size(data, domains, nr_domains),
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GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->drvdata = d;
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bank = d->pin_banks;
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nr_domains = 0;
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for (i = 0; i < d->nr_banks; ++i, ++bank) {
|
|
if (bank->eint_type != EINT_TYPE_GPIO)
|
|
continue;
|
|
|
|
data->domains[nr_domains++] = bank->irq_domain;
|
|
}
|
|
|
|
irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Functions for configuration of EINT0 wake-up interrupts
|
|
*/
|
|
|
|
static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
|
|
{
|
|
struct s3c64xx_eint0_domain_data *ddata =
|
|
irq_data_get_irq_chip_data(irqd);
|
|
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
|
|
u32 val;
|
|
|
|
val = readl(d->virt_base + EINT0MASK_REG);
|
|
if (mask)
|
|
val |= 1 << ddata->eints[irqd->hwirq];
|
|
else
|
|
val &= ~(1 << ddata->eints[irqd->hwirq]);
|
|
writel(val, d->virt_base + EINT0MASK_REG);
|
|
}
|
|
|
|
static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
|
|
{
|
|
s3c64xx_eint0_irq_set_mask(irqd, false);
|
|
}
|
|
|
|
static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
|
|
{
|
|
s3c64xx_eint0_irq_set_mask(irqd, true);
|
|
}
|
|
|
|
static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
|
|
{
|
|
struct s3c64xx_eint0_domain_data *ddata =
|
|
irq_data_get_irq_chip_data(irqd);
|
|
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
|
|
|
|
writel(1 << ddata->eints[irqd->hwirq],
|
|
d->virt_base + EINT0PEND_REG);
|
|
}
|
|
|
|
static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
|
|
{
|
|
struct s3c64xx_eint0_domain_data *ddata =
|
|
irq_data_get_irq_chip_data(irqd);
|
|
struct samsung_pin_bank *bank = ddata->bank;
|
|
struct samsung_pinctrl_drv_data *d = bank->drvdata;
|
|
void __iomem *reg;
|
|
int trigger;
|
|
u8 shift;
|
|
u32 val;
|
|
|
|
trigger = s3c64xx_irq_get_trigger(type);
|
|
if (trigger < 0) {
|
|
pr_err("unsupported external interrupt type\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
s3c64xx_irq_set_handler(irqd, type);
|
|
|
|
/* Set up interrupt trigger */
|
|
reg = d->virt_base + EINT0CON0_REG;
|
|
shift = ddata->eints[irqd->hwirq];
|
|
if (shift >= EINT_MAX_PER_REG) {
|
|
reg += 4;
|
|
shift -= EINT_MAX_PER_REG;
|
|
}
|
|
shift = EINT_CON_LEN * (shift / 2);
|
|
|
|
val = readl(reg);
|
|
val &= ~(EINT_CON_MASK << shift);
|
|
val |= trigger << shift;
|
|
writel(val, reg);
|
|
|
|
s3c64xx_irq_set_function(d, bank, irqd->hwirq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* irq_chip for wakeup interrupts
|
|
*/
|
|
static struct irq_chip s3c64xx_eint0_irq_chip = {
|
|
.name = "EINT0",
|
|
.irq_unmask = s3c64xx_eint0_irq_unmask,
|
|
.irq_mask = s3c64xx_eint0_irq_mask,
|
|
.irq_ack = s3c64xx_eint0_irq_ack,
|
|
.irq_set_type = s3c64xx_eint0_irq_set_type,
|
|
};
|
|
|
|
static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
|
|
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
|
|
unsigned int pend, mask;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
pend = readl(drvdata->virt_base + EINT0PEND_REG);
|
|
mask = readl(drvdata->virt_base + EINT0MASK_REG);
|
|
|
|
pend = pend & range & ~mask;
|
|
pend &= range;
|
|
|
|
while (pend) {
|
|
unsigned int irq;
|
|
int ret;
|
|
|
|
irq = fls(pend) - 1;
|
|
pend &= ~(1 << irq);
|
|
ret = generic_handle_domain_irq(data->domains[irq], data->pins[irq]);
|
|
/*
|
|
* Something must be really wrong if an unmapped EINT
|
|
* was unmasked...
|
|
*/
|
|
BUG_ON(ret);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
|
|
{
|
|
s3c64xx_irq_demux_eint(desc, 0xf);
|
|
}
|
|
|
|
static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
|
|
{
|
|
s3c64xx_irq_demux_eint(desc, 0xff0);
|
|
}
|
|
|
|
static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
|
|
{
|
|
s3c64xx_irq_demux_eint(desc, 0xff000);
|
|
}
|
|
|
|
static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
|
|
{
|
|
s3c64xx_irq_demux_eint(desc, 0xff00000);
|
|
}
|
|
|
|
static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
|
|
s3c64xx_demux_eint0_3,
|
|
s3c64xx_demux_eint4_11,
|
|
s3c64xx_demux_eint12_19,
|
|
s3c64xx_demux_eint20_27,
|
|
};
|
|
|
|
static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
struct s3c64xx_eint0_domain_data *ddata = h->host_data;
|
|
struct samsung_pin_bank *bank = ddata->bank;
|
|
|
|
if (!(bank->eint_mask & (1 << hw)))
|
|
return -EINVAL;
|
|
|
|
irq_set_chip_and_handler(virq,
|
|
&s3c64xx_eint0_irq_chip, handle_level_irq);
|
|
irq_set_chip_data(virq, ddata);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* irq domain callbacks for external wakeup interrupt controller.
|
|
*/
|
|
static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
|
|
.map = s3c64xx_eint0_irq_map,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
/* list of external wakeup controllers supported */
|
|
static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
|
|
{ .compatible = "samsung,s3c64xx-wakeup-eint", },
|
|
{ }
|
|
};
|
|
|
|
/**
|
|
* s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
|
|
* @d: driver data of samsung pinctrl driver.
|
|
*/
|
|
static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
|
|
{
|
|
struct device *dev = d->dev;
|
|
struct device_node *eint0_np = NULL;
|
|
struct device_node *np;
|
|
struct samsung_pin_bank *bank;
|
|
struct s3c64xx_eint0_data *data;
|
|
unsigned int i;
|
|
|
|
for_each_child_of_node(dev->of_node, np) {
|
|
if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
|
|
eint0_np = np;
|
|
break;
|
|
}
|
|
}
|
|
if (!eint0_np)
|
|
return -ENODEV;
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data) {
|
|
of_node_put(eint0_np);
|
|
return -ENOMEM;
|
|
}
|
|
data->drvdata = d;
|
|
|
|
for (i = 0; i < NUM_EINT0_IRQ; ++i) {
|
|
unsigned int irq;
|
|
|
|
irq = irq_of_parse_and_map(eint0_np, i);
|
|
if (!irq) {
|
|
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
|
|
of_node_put(eint0_np);
|
|
return -ENXIO;
|
|
}
|
|
|
|
irq_set_chained_handler_and_data(irq,
|
|
s3c64xx_eint0_handlers[i],
|
|
data);
|
|
}
|
|
of_node_put(eint0_np);
|
|
|
|
bank = d->pin_banks;
|
|
for (i = 0; i < d->nr_banks; ++i, ++bank) {
|
|
struct s3c64xx_eint0_domain_data *ddata;
|
|
unsigned int nr_eints;
|
|
unsigned int mask;
|
|
unsigned int irq;
|
|
unsigned int pin;
|
|
|
|
if (bank->eint_type != EINT_TYPE_WKUP)
|
|
continue;
|
|
|
|
mask = bank->eint_mask;
|
|
nr_eints = fls(mask);
|
|
|
|
ddata = devm_kzalloc(dev,
|
|
sizeof(*ddata) + nr_eints, GFP_KERNEL);
|
|
if (!ddata)
|
|
return -ENOMEM;
|
|
ddata->bank = bank;
|
|
|
|
bank->irq_domain = irq_domain_create_linear(bank->fwnode,
|
|
nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
|
|
if (!bank->irq_domain) {
|
|
dev_err(dev, "wkup irq domain add failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
irq = bank->eint_offset;
|
|
mask = bank->eint_mask;
|
|
for (pin = 0; mask; ++pin, mask >>= 1) {
|
|
if (!(mask & 1))
|
|
continue;
|
|
data->domains[irq] = bank->irq_domain;
|
|
data->pins[irq] = pin;
|
|
ddata->eints[pin] = irq;
|
|
++irq;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* pin banks of s3c64xx pin-controller 0 */
|
|
static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
|
|
PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
|
|
PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
|
|
PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
|
|
PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
|
|
PIN_BANK_4BIT(5, 0x080, "gpe"),
|
|
PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
|
|
PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
|
|
PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
|
|
PIN_BANK_2BIT(16, 0x100, "gpi"),
|
|
PIN_BANK_2BIT(12, 0x120, "gpj"),
|
|
PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
|
|
PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
|
|
PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
|
|
PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
|
|
PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
|
|
PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
|
|
PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
|
|
* one gpio/pin-mux/pinconfig controller.
|
|
*/
|
|
static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
|
|
{
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = s3c64xx_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
|
|
.eint_gpio_init = s3c64xx_eint_gpio_init,
|
|
.eint_wkup_init = s3c64xx_eint_eint0_init,
|
|
},
|
|
};
|
|
|
|
const struct samsung_pinctrl_of_match_data s3c64xx_of_data __initconst = {
|
|
.ctrl = s3c64xx_pin_ctrl,
|
|
.num_ctrl = ARRAY_SIZE(s3c64xx_pin_ctrl),
|
|
};
|