421 lines
11 KiB
C
421 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Platform Management Framework Driver
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*
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* Copyright (c) 2022, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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*/
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#ifndef PMF_H
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#define PMF_H
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#include <linux/acpi.h>
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#include <linux/platform_profile.h>
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/* APMF Functions */
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#define APMF_FUNC_VERIFY_INTERFACE 0
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#define APMF_FUNC_GET_SYS_PARAMS 1
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#define APMF_FUNC_SBIOS_REQUESTS 2
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#define APMF_FUNC_SBIOS_HEARTBEAT 4
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#define APMF_FUNC_AUTO_MODE 5
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#define APMF_FUNC_SET_FAN_IDX 7
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#define APMF_FUNC_STATIC_SLIDER_GRANULAR 9
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#define APMF_FUNC_DYN_SLIDER_AC 11
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#define APMF_FUNC_DYN_SLIDER_DC 12
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/* Message Definitions */
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#define SET_SPL 0x03 /* SPL: Sustained Power Limit */
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#define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */
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#define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */
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#define GET_SPL 0x0B
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#define GET_SPPT 0x0D
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#define GET_FPPT 0x0F
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#define SET_DRAM_ADDR_HIGH 0x14
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#define SET_DRAM_ADDR_LOW 0x15
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#define SET_TRANSFER_TABLE 0x16
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#define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */
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#define SET_STT_LIMIT_APU 0x19
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#define SET_STT_LIMIT_HS2 0x1A
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#define SET_SPPT_APU_ONLY 0x1D
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#define GET_SPPT_APU_ONLY 0x1E
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#define GET_STT_MIN_LIMIT 0x1F
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#define GET_STT_LIMIT_APU 0x20
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#define GET_STT_LIMIT_HS2 0x21
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/* Fan Index for Auto Mode */
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#define FAN_INDEX_AUTO 0xFFFFFFFF
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#define ARG_NONE 0
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#define AVG_SAMPLE_SIZE 3
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/* AMD PMF BIOS interfaces */
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struct apmf_verify_interface {
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u16 size;
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u16 version;
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u32 notification_mask;
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u32 supported_functions;
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} __packed;
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struct apmf_system_params {
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u16 size;
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u32 valid_mask;
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u32 flags;
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u8 command_code;
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u32 heartbeat_int;
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} __packed;
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struct apmf_sbios_req {
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u16 size;
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u32 pending_req;
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u8 rsd;
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u8 cql_event;
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u8 amt_event;
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u32 fppt;
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u32 sppt;
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u32 fppt_apu_only;
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u32 spl;
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u32 stt_min_limit;
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u8 skin_temp_apu;
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u8 skin_temp_hs2;
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} __packed;
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struct apmf_fan_idx {
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u16 size;
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u8 fan_ctl_mode;
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u32 fan_ctl_idx;
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} __packed;
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struct smu_pmf_metrics {
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u16 gfxclk_freq; /* in MHz */
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u16 socclk_freq; /* in MHz */
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u16 vclk_freq; /* in MHz */
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u16 dclk_freq; /* in MHz */
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u16 memclk_freq; /* in MHz */
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u16 spare;
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u16 gfx_activity; /* in Centi */
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u16 uvd_activity; /* in Centi */
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u16 voltage[2]; /* in mV */
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u16 currents[2]; /* in mA */
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u16 power[2];/* in mW */
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u16 core_freq[8]; /* in MHz */
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u16 core_power[8]; /* in mW */
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u16 core_temp[8]; /* in centi-Celsius */
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u16 l3_freq; /* in MHz */
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u16 l3_temp; /* in centi-Celsius */
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u16 gfx_temp; /* in centi-Celsius */
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u16 soc_temp; /* in centi-Celsius */
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u16 throttler_status;
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u16 current_socketpower; /* in mW */
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u16 stapm_orig_limit; /* in W */
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u16 stapm_cur_limit; /* in W */
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u32 apu_power; /* in mW */
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u32 dgpu_power; /* in mW */
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u16 vdd_tdc_val; /* in mA */
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u16 soc_tdc_val; /* in mA */
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u16 vdd_edc_val; /* in mA */
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u16 soc_edcv_al; /* in mA */
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u16 infra_cpu_maxfreq; /* in MHz */
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u16 infra_gfx_maxfreq; /* in MHz */
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u16 skin_temp; /* in centi-Celsius */
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u16 device_state;
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} __packed;
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enum amd_stt_skin_temp {
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STT_TEMP_APU,
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STT_TEMP_HS2,
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STT_TEMP_COUNT,
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};
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enum amd_slider_op {
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SLIDER_OP_GET,
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SLIDER_OP_SET,
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};
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enum power_source {
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POWER_SOURCE_AC,
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POWER_SOURCE_DC,
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POWER_SOURCE_MAX,
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};
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enum power_modes {
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POWER_MODE_PERFORMANCE,
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POWER_MODE_BALANCED_POWER,
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POWER_MODE_POWER_SAVER,
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POWER_MODE_MAX,
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};
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struct amd_pmf_dev {
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void __iomem *regbase;
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void __iomem *smu_virt_addr;
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void *buf;
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u32 base_addr;
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u32 cpu_id;
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struct device *dev;
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struct mutex lock; /* protects the PMF interface */
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u32 supported_func;
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enum platform_profile_option current_profile;
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struct platform_profile_handler pprof;
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struct dentry *dbgfs_dir;
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int hb_interval; /* SBIOS heartbeat interval */
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struct delayed_work heart_beat;
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struct smu_pmf_metrics m_table;
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struct delayed_work work_buffer;
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ktime_t start_time;
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int socket_power_history[AVG_SAMPLE_SIZE];
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int socket_power_history_idx;
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bool amt_enabled;
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struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
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bool cnqf_enabled;
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bool cnqf_supported;
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struct notifier_block pwr_src_notifier;
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};
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struct apmf_sps_prop_granular {
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u32 fppt;
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u32 sppt;
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u32 sppt_apu_only;
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u32 spl;
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u32 stt_min;
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u8 stt_skin_temp[STT_TEMP_COUNT];
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u32 fan_id;
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} __packed;
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/* Static Slider */
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struct apmf_static_slider_granular_output {
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u16 size;
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struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
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} __packed;
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struct amd_pmf_static_slider_granular {
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u16 size;
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struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
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};
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struct fan_table_control {
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bool manual;
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unsigned long fan_id;
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};
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struct power_table_control {
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u32 spl;
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u32 sppt;
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u32 fppt;
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u32 sppt_apu_only;
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u32 stt_min;
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u32 stt_skin_temp[STT_TEMP_COUNT];
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u32 reserved[16];
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};
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/* Auto Mode Layer */
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enum auto_mode_transition_priority {
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AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
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AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
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AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
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AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
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AUTO_TRANSITION_MAX,
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};
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enum auto_mode_mode {
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AUTO_QUIET,
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AUTO_BALANCE,
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AUTO_PERFORMANCE_ON_LAP,
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AUTO_PERFORMANCE,
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AUTO_MODE_MAX,
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};
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struct auto_mode_trans_params {
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u32 time_constant; /* minimum time required to switch to next mode */
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u32 power_delta; /* delta power to shift mode */
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u32 power_threshold;
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u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
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u32 applied;
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enum auto_mode_mode target_mode;
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u32 shifting_up;
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};
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struct auto_mode_mode_settings {
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struct power_table_control power_control;
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struct fan_table_control fan_control;
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u32 power_floor;
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};
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struct auto_mode_mode_config {
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struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
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struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
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enum auto_mode_mode current_mode;
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};
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struct apmf_auto_mode {
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u16 size;
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/* time constant */
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u32 balanced_to_perf;
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u32 perf_to_balanced;
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u32 quiet_to_balanced;
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u32 balanced_to_quiet;
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/* power floor */
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u32 pfloor_perf;
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u32 pfloor_balanced;
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u32 pfloor_quiet;
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/* Power delta for mode change */
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u32 pd_balanced_to_perf;
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u32 pd_perf_to_balanced;
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u32 pd_quiet_to_balanced;
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u32 pd_balanced_to_quiet;
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/* skin temperature limits */
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u8 stt_apu_perf_on_lap; /* CQL ON */
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u8 stt_hs2_perf_on_lap; /* CQL ON */
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u8 stt_apu_perf;
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u8 stt_hs2_perf;
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u8 stt_apu_balanced;
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u8 stt_hs2_balanced;
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u8 stt_apu_quiet;
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u8 stt_hs2_quiet;
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u32 stt_min_limit_perf_on_lap; /* CQL ON */
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u32 stt_min_limit_perf;
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u32 stt_min_limit_balanced;
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u32 stt_min_limit_quiet;
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/* SPL based */
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u32 fppt_perf_on_lap; /* CQL ON */
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u32 sppt_perf_on_lap; /* CQL ON */
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u32 spl_perf_on_lap; /* CQL ON */
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u32 sppt_apu_only_perf_on_lap; /* CQL ON */
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u32 fppt_perf;
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u32 sppt_perf;
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u32 spl_perf;
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u32 sppt_apu_only_perf;
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u32 fppt_balanced;
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u32 sppt_balanced;
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u32 spl_balanced;
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u32 sppt_apu_only_balanced;
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u32 fppt_quiet;
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u32 sppt_quiet;
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u32 spl_quiet;
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u32 sppt_apu_only_quiet;
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/* Fan ID */
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u32 fan_id_perf;
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u32 fan_id_balanced;
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u32 fan_id_quiet;
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} __packed;
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/* CnQF Layer */
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enum cnqf_trans_priority {
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CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
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CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
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CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
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CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
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CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
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CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
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CNQF_TRANSITION_MAX,
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};
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enum cnqf_mode {
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CNQF_MODE_QUIET,
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CNQF_MODE_BALANCE,
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CNQF_MODE_PERFORMANCE,
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CNQF_MODE_TURBO,
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CNQF_MODE_MAX,
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};
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enum apmf_cnqf_pos {
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APMF_CNQF_TURBO,
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APMF_CNQF_PERFORMANCE,
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APMF_CNQF_BALANCE,
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APMF_CNQF_QUIET,
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APMF_CNQF_MAX,
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};
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struct cnqf_mode_settings {
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struct power_table_control power_control;
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struct fan_table_control fan_control;
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u32 power_floor;
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};
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struct cnqf_tran_params {
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u32 time_constant; /* minimum time required to switch to next mode */
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u32 power_threshold;
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u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
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u32 total_power;
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u32 count;
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bool priority;
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bool shifting_up;
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enum cnqf_mode target_mode;
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};
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struct cnqf_config {
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struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
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struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
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struct power_table_control defaults;
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enum cnqf_mode current_mode;
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u32 power_src;
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u32 avg_power;
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};
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struct apmf_cnqf_power_set {
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u32 pfloor;
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u32 fppt;
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u32 sppt;
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u32 sppt_apu_only;
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u32 spl;
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u32 stt_min_limit;
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u8 stt_skintemp[STT_TEMP_COUNT];
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u32 fan_id;
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} __packed;
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struct apmf_dyn_slider_output {
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u16 size;
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u16 flags;
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u32 t_perf_to_turbo;
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u32 t_balanced_to_perf;
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u32 t_quiet_to_balanced;
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u32 t_balanced_to_quiet;
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u32 t_perf_to_balanced;
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u32 t_turbo_to_perf;
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struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
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} __packed;
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/* Core Layer */
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int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
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void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
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int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
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int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
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int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
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int amd_pmf_get_power_source(void);
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int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
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/* SPS Layer */
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int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
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void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
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struct amd_pmf_static_slider_granular *table);
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int amd_pmf_init_sps(struct amd_pmf_dev *dev);
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void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
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int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
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struct apmf_static_slider_granular_output *output);
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bool is_pprof_balanced(struct amd_pmf_dev *pmf);
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int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
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int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
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/* Auto Mode Layer */
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int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
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void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
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void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
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void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
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int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
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void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
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int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
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void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
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/* CnQF Layer */
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int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
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int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
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int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
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void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
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int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
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extern const struct attribute_group cnqf_feature_attribute_group;
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#endif /* PMF_H */
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