893 lines
21 KiB
C
893 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Derived from many drivers using generic_serial interface.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*
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* Serial driver for BCM63xx integrated UART.
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*
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* Hardware flow control was _not_ tested since I only have RX/TX on
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* my board.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/console.h>
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#include <linux/clk.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/sysrq.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_bcm63xx.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#define BCM63XX_NR_UARTS 2
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static struct uart_port ports[BCM63XX_NR_UARTS];
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/*
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* rx interrupt mask / stat
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*
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* mask:
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* - rx fifo full
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* - rx fifo above threshold
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* - rx fifo not empty for too long
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*/
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#define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
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UART_IR_MASK(UART_IR_RXTHRESH) | \
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UART_IR_MASK(UART_IR_RXTIMEOUT))
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#define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
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UART_IR_STAT(UART_IR_RXTHRESH) | \
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UART_IR_STAT(UART_IR_RXTIMEOUT))
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/*
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* tx interrupt mask / stat
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*
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* mask:
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* - tx fifo empty
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* - tx fifo below threshold
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*/
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#define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
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UART_IR_MASK(UART_IR_TXTRESH))
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#define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
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UART_IR_STAT(UART_IR_TXTRESH))
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/*
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* external input interrupt
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*
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* mask: any edge on CTS, DCD
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*/
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#define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
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UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
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/*
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* handy uart register accessor
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*/
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static inline unsigned int bcm_uart_readl(struct uart_port *port,
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unsigned int offset)
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{
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return __raw_readl(port->membase + offset);
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}
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static inline void bcm_uart_writel(struct uart_port *port,
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unsigned int value, unsigned int offset)
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{
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__raw_writel(value, port->membase + offset);
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}
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/*
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* serial core request to check if uart tx fifo is empty
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*/
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static unsigned int bcm_uart_tx_empty(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_IR_REG);
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return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
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}
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/*
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* serial core request to set RTS and DTR pin state and loopback mode
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*/
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static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_MCTL_REG);
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val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
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/* invert of written value is reflected on the pin */
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if (!(mctrl & TIOCM_DTR))
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val |= UART_MCTL_DTR_MASK;
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if (!(mctrl & TIOCM_RTS))
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val |= UART_MCTL_RTS_MASK;
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bcm_uart_writel(port, val, UART_MCTL_REG);
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val = bcm_uart_readl(port, UART_CTL_REG);
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if (mctrl & TIOCM_LOOP)
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val |= UART_CTL_LOOPBACK_MASK;
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else
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val &= ~UART_CTL_LOOPBACK_MASK;
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bcm_uart_writel(port, val, UART_CTL_REG);
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}
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/*
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* serial core request to return RI, CTS, DCD and DSR pin state
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*/
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static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
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{
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unsigned int val, mctrl;
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mctrl = 0;
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val = bcm_uart_readl(port, UART_EXTINP_REG);
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if (val & UART_EXTINP_RI_MASK)
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mctrl |= TIOCM_RI;
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if (val & UART_EXTINP_CTS_MASK)
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mctrl |= TIOCM_CTS;
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if (val & UART_EXTINP_DCD_MASK)
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mctrl |= TIOCM_CD;
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if (val & UART_EXTINP_DSR_MASK)
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mctrl |= TIOCM_DSR;
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return mctrl;
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}
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/*
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* serial core request to disable tx ASAP (used for flow control)
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*/
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static void bcm_uart_stop_tx(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_CTL_REG);
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val &= ~(UART_CTL_TXEN_MASK);
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bcm_uart_writel(port, val, UART_CTL_REG);
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val = bcm_uart_readl(port, UART_IR_REG);
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val &= ~UART_TX_INT_MASK;
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bcm_uart_writel(port, val, UART_IR_REG);
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}
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/*
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* serial core request to (re)enable tx
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*/
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static void bcm_uart_start_tx(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_IR_REG);
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val |= UART_TX_INT_MASK;
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bcm_uart_writel(port, val, UART_IR_REG);
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val = bcm_uart_readl(port, UART_CTL_REG);
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val |= UART_CTL_TXEN_MASK;
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bcm_uart_writel(port, val, UART_CTL_REG);
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}
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/*
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* serial core request to stop rx, called before port shutdown
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*/
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static void bcm_uart_stop_rx(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_IR_REG);
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val &= ~UART_RX_INT_MASK;
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bcm_uart_writel(port, val, UART_IR_REG);
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}
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/*
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* serial core request to enable modem status interrupt reporting
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*/
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static void bcm_uart_enable_ms(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_IR_REG);
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val |= UART_IR_MASK(UART_IR_EXTIP);
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bcm_uart_writel(port, val, UART_IR_REG);
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}
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/*
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* serial core request to start/stop emitting break char
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*/
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static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
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{
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unsigned long flags;
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unsigned int val;
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spin_lock_irqsave(&port->lock, flags);
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val = bcm_uart_readl(port, UART_CTL_REG);
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if (ctl)
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val |= UART_CTL_XMITBRK_MASK;
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else
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val &= ~UART_CTL_XMITBRK_MASK;
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bcm_uart_writel(port, val, UART_CTL_REG);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/*
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* return port type in string format
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*/
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static const char *bcm_uart_type(struct uart_port *port)
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{
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return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
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}
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/*
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* read all chars in rx fifo and send them to core
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*/
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static void bcm_uart_do_rx(struct uart_port *port)
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{
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struct tty_port *tty_port = &port->state->port;
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unsigned int max_count;
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/* limit number of char read in interrupt, should not be
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* higher than fifo size anyway since we're much faster than
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* serial port */
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max_count = 32;
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do {
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unsigned int iestat, c, cstat;
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char flag;
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/* get overrun/fifo empty information from ier
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* register */
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iestat = bcm_uart_readl(port, UART_IR_REG);
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if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
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unsigned int val;
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/* fifo reset is required to clear
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* interrupt */
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val = bcm_uart_readl(port, UART_CTL_REG);
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val |= UART_CTL_RSTRXFIFO_MASK;
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bcm_uart_writel(port, val, UART_CTL_REG);
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port->icount.overrun++;
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tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
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}
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if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
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break;
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cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
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port->icount.rx++;
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flag = TTY_NORMAL;
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c &= 0xff;
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if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
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/* do stats first */
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if (cstat & UART_FIFO_BRKDET_MASK) {
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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}
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if (cstat & UART_FIFO_PARERR_MASK)
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port->icount.parity++;
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if (cstat & UART_FIFO_FRAMEERR_MASK)
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port->icount.frame++;
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/* update flag wrt read_status_mask */
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cstat &= port->read_status_mask;
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if (cstat & UART_FIFO_BRKDET_MASK)
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flag = TTY_BREAK;
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if (cstat & UART_FIFO_FRAMEERR_MASK)
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flag = TTY_FRAME;
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if (cstat & UART_FIFO_PARERR_MASK)
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flag = TTY_PARITY;
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}
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if (uart_handle_sysrq_char(port, c))
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continue;
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if ((cstat & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tty_port, c, flag);
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} while (--max_count);
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tty_flip_buffer_push(tty_port);
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}
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/*
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* fill tx fifo with chars to send, stop when fifo is about to be full
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* or when all chars have been sent.
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*/
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static void bcm_uart_do_tx(struct uart_port *port)
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{
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unsigned int val;
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bool pending;
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u8 ch;
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val = bcm_uart_readl(port, UART_MCTL_REG);
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val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
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pending = uart_port_tx_limited(port, ch, port->fifosize - val,
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true,
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bcm_uart_writel(port, ch, UART_FIFO_REG),
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({}));
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if (pending)
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return;
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/* nothing to send, disable transmit interrupt */
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val = bcm_uart_readl(port, UART_IR_REG);
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val &= ~UART_TX_INT_MASK;
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bcm_uart_writel(port, val, UART_IR_REG);
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}
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/*
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* process uart interrupt
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*/
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static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
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{
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struct uart_port *port;
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unsigned int irqstat;
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port = dev_id;
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spin_lock(&port->lock);
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irqstat = bcm_uart_readl(port, UART_IR_REG);
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if (irqstat & UART_RX_INT_STAT)
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bcm_uart_do_rx(port);
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if (irqstat & UART_TX_INT_STAT)
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bcm_uart_do_tx(port);
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if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
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unsigned int estat;
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estat = bcm_uart_readl(port, UART_EXTINP_REG);
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if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
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uart_handle_cts_change(port,
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estat & UART_EXTINP_CTS_MASK);
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if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
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uart_handle_dcd_change(port,
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estat & UART_EXTINP_DCD_MASK);
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}
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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/*
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* enable rx & tx operation on uart
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*/
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static void bcm_uart_enable(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_CTL_REG);
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val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
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bcm_uart_writel(port, val, UART_CTL_REG);
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}
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/*
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* disable rx & tx operation on uart
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*/
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static void bcm_uart_disable(struct uart_port *port)
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{
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unsigned int val;
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val = bcm_uart_readl(port, UART_CTL_REG);
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val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
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UART_CTL_RXEN_MASK);
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bcm_uart_writel(port, val, UART_CTL_REG);
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}
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/*
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* clear all unread data in rx fifo and unsent data in tx fifo
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*/
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static void bcm_uart_flush(struct uart_port *port)
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{
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unsigned int val;
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/* empty rx and tx fifo */
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val = bcm_uart_readl(port, UART_CTL_REG);
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val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
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bcm_uart_writel(port, val, UART_CTL_REG);
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/* read any pending char to make sure all irq status are
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* cleared */
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(void)bcm_uart_readl(port, UART_FIFO_REG);
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}
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/*
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* serial core request to initialize uart and start rx operation
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*/
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static int bcm_uart_startup(struct uart_port *port)
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{
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unsigned int val;
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int ret;
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/* mask all irq and flush port */
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bcm_uart_disable(port);
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bcm_uart_writel(port, 0, UART_IR_REG);
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bcm_uart_flush(port);
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/* clear any pending external input interrupt */
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(void)bcm_uart_readl(port, UART_EXTINP_REG);
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/* set rx/tx fifo thresh to fifo half size */
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val = bcm_uart_readl(port, UART_MCTL_REG);
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val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
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val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
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val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
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bcm_uart_writel(port, val, UART_MCTL_REG);
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/* set rx fifo timeout to 1 char time */
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val = bcm_uart_readl(port, UART_CTL_REG);
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val &= ~UART_CTL_RXTMOUTCNT_MASK;
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val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
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bcm_uart_writel(port, val, UART_CTL_REG);
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/* report any edge on dcd and cts */
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val = UART_EXTINP_INT_MASK;
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val |= UART_EXTINP_DCD_NOSENSE_MASK;
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val |= UART_EXTINP_CTS_NOSENSE_MASK;
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bcm_uart_writel(port, val, UART_EXTINP_REG);
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/* register irq and enable rx interrupts */
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ret = request_irq(port->irq, bcm_uart_interrupt, 0,
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dev_name(port->dev), port);
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if (ret)
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return ret;
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bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
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bcm_uart_enable(port);
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return 0;
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}
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/*
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* serial core request to flush & disable uart
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*/
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static void bcm_uart_shutdown(struct uart_port *port)
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{
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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bcm_uart_writel(port, 0, UART_IR_REG);
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spin_unlock_irqrestore(&port->lock, flags);
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bcm_uart_disable(port);
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bcm_uart_flush(port);
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free_irq(port->irq, port);
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}
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/*
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* serial core request to change current uart setting
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*/
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static void bcm_uart_set_termios(struct uart_port *port, struct ktermios *new,
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const struct ktermios *old)
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{
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unsigned int ctl, baud, quot, ier;
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unsigned long flags;
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int tries;
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spin_lock_irqsave(&port->lock, flags);
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/* Drain the hot tub fully before we power it off for the winter. */
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for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
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mdelay(10);
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/* disable uart while changing speed */
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bcm_uart_disable(port);
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bcm_uart_flush(port);
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/* update Control register */
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ctl = bcm_uart_readl(port, UART_CTL_REG);
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ctl &= ~UART_CTL_BITSPERSYM_MASK;
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switch (new->c_cflag & CSIZE) {
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case CS5:
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ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
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break;
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case CS6:
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ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
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break;
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case CS7:
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ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
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break;
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default:
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ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
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break;
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}
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ctl &= ~UART_CTL_STOPBITS_MASK;
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if (new->c_cflag & CSTOPB)
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ctl |= UART_CTL_STOPBITS_2;
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else
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ctl |= UART_CTL_STOPBITS_1;
|
|
|
|
ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
|
|
if (new->c_cflag & PARENB)
|
|
ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
|
|
ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
|
|
if (new->c_cflag & PARODD)
|
|
ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
|
|
bcm_uart_writel(port, ctl, UART_CTL_REG);
|
|
|
|
/* update Baudword register */
|
|
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
|
|
quot = uart_get_divisor(port, baud) - 1;
|
|
bcm_uart_writel(port, quot, UART_BAUD_REG);
|
|
|
|
/* update Interrupt register */
|
|
ier = bcm_uart_readl(port, UART_IR_REG);
|
|
|
|
ier &= ~UART_IR_MASK(UART_IR_EXTIP);
|
|
if (UART_ENABLE_MS(port, new->c_cflag))
|
|
ier |= UART_IR_MASK(UART_IR_EXTIP);
|
|
|
|
bcm_uart_writel(port, ier, UART_IR_REG);
|
|
|
|
/* update read/ignore mask */
|
|
port->read_status_mask = UART_FIFO_VALID_MASK;
|
|
if (new->c_iflag & INPCK) {
|
|
port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
|
|
port->read_status_mask |= UART_FIFO_PARERR_MASK;
|
|
}
|
|
if (new->c_iflag & (IGNBRK | BRKINT))
|
|
port->read_status_mask |= UART_FIFO_BRKDET_MASK;
|
|
|
|
port->ignore_status_mask = 0;
|
|
if (new->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
|
|
if (new->c_iflag & IGNBRK)
|
|
port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
|
|
if (!(new->c_cflag & CREAD))
|
|
port->ignore_status_mask |= UART_FIFO_VALID_MASK;
|
|
|
|
uart_update_timeout(port, new->c_cflag, baud);
|
|
bcm_uart_enable(port);
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
/*
|
|
* serial core request to claim uart iomem
|
|
*/
|
|
static int bcm_uart_request_port(struct uart_port *port)
|
|
{
|
|
/* UARTs always present */
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* serial core request to release uart iomem
|
|
*/
|
|
static void bcm_uart_release_port(struct uart_port *port)
|
|
{
|
|
/* Nothing to release ... */
|
|
}
|
|
|
|
/*
|
|
* serial core request to do any port required autoconfiguration
|
|
*/
|
|
static void bcm_uart_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
if (bcm_uart_request_port(port))
|
|
return;
|
|
port->type = PORT_BCM63XX;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* serial core request to check that port information in serinfo are
|
|
* suitable
|
|
*/
|
|
static int bcm_uart_verify_port(struct uart_port *port,
|
|
struct serial_struct *serinfo)
|
|
{
|
|
if (port->type != PORT_BCM63XX)
|
|
return -EINVAL;
|
|
if (port->irq != serinfo->irq)
|
|
return -EINVAL;
|
|
if (port->iotype != serinfo->io_type)
|
|
return -EINVAL;
|
|
if (port->mapbase != (unsigned long)serinfo->iomem_base)
|
|
return -EINVAL;
|
|
return 0;
|
|
}
|
|
|
|
/* serial core callbacks */
|
|
static const struct uart_ops bcm_uart_ops = {
|
|
.tx_empty = bcm_uart_tx_empty,
|
|
.get_mctrl = bcm_uart_get_mctrl,
|
|
.set_mctrl = bcm_uart_set_mctrl,
|
|
.start_tx = bcm_uart_start_tx,
|
|
.stop_tx = bcm_uart_stop_tx,
|
|
.stop_rx = bcm_uart_stop_rx,
|
|
.enable_ms = bcm_uart_enable_ms,
|
|
.break_ctl = bcm_uart_break_ctl,
|
|
.startup = bcm_uart_startup,
|
|
.shutdown = bcm_uart_shutdown,
|
|
.set_termios = bcm_uart_set_termios,
|
|
.type = bcm_uart_type,
|
|
.release_port = bcm_uart_release_port,
|
|
.request_port = bcm_uart_request_port,
|
|
.config_port = bcm_uart_config_port,
|
|
.verify_port = bcm_uart_verify_port,
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
|
|
static void wait_for_xmitr(struct uart_port *port)
|
|
{
|
|
unsigned int tmout;
|
|
|
|
/* Wait up to 10ms for the character(s) to be sent. */
|
|
tmout = 10000;
|
|
while (--tmout) {
|
|
unsigned int val;
|
|
|
|
val = bcm_uart_readl(port, UART_IR_REG);
|
|
if (val & UART_IR_STAT(UART_IR_TXEMPTY))
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
/* Wait up to 1s for flow control if necessary */
|
|
if (port->flags & UPF_CONS_FLOW) {
|
|
tmout = 1000000;
|
|
while (--tmout) {
|
|
unsigned int val;
|
|
|
|
val = bcm_uart_readl(port, UART_EXTINP_REG);
|
|
if (val & UART_EXTINP_CTS_MASK)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* output given char
|
|
*/
|
|
static void bcm_console_putchar(struct uart_port *port, unsigned char ch)
|
|
{
|
|
wait_for_xmitr(port);
|
|
bcm_uart_writel(port, ch, UART_FIFO_REG);
|
|
}
|
|
|
|
/*
|
|
* console core request to output given string
|
|
*/
|
|
static void bcm_console_write(struct console *co, const char *s,
|
|
unsigned int count)
|
|
{
|
|
struct uart_port *port;
|
|
unsigned long flags;
|
|
int locked;
|
|
|
|
port = &ports[co->index];
|
|
|
|
local_irq_save(flags);
|
|
if (port->sysrq) {
|
|
/* bcm_uart_interrupt() already took the lock */
|
|
locked = 0;
|
|
} else if (oops_in_progress) {
|
|
locked = spin_trylock(&port->lock);
|
|
} else {
|
|
spin_lock(&port->lock);
|
|
locked = 1;
|
|
}
|
|
|
|
/* call helper to deal with \r\n */
|
|
uart_console_write(port, s, count, bcm_console_putchar);
|
|
|
|
/* and wait for char to be transmitted */
|
|
wait_for_xmitr(port);
|
|
|
|
if (locked)
|
|
spin_unlock(&port->lock);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/*
|
|
* console core request to setup given console, find matching uart
|
|
* port and setup it.
|
|
*/
|
|
static int bcm_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_port *port;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
|
|
return -EINVAL;
|
|
port = &ports[co->index];
|
|
if (!port->membase)
|
|
return -ENODEV;
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver bcm_uart_driver;
|
|
|
|
static struct console bcm63xx_console = {
|
|
.name = "ttyS",
|
|
.write = bcm_console_write,
|
|
.device = uart_console_device,
|
|
.setup = bcm_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &bcm_uart_driver,
|
|
};
|
|
|
|
static int __init bcm63xx_console_init(void)
|
|
{
|
|
register_console(&bcm63xx_console);
|
|
return 0;
|
|
}
|
|
|
|
console_initcall(bcm63xx_console_init);
|
|
|
|
static void bcm_early_write(struct console *con, const char *s, unsigned n)
|
|
{
|
|
struct earlycon_device *dev = con->data;
|
|
|
|
uart_console_write(&dev->port, s, n, bcm_console_putchar);
|
|
wait_for_xmitr(&dev->port);
|
|
}
|
|
|
|
static int __init bcm_early_console_setup(struct earlycon_device *device,
|
|
const char *opt)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
device->con->write = bcm_early_write;
|
|
return 0;
|
|
}
|
|
|
|
OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
|
|
|
|
#define BCM63XX_CONSOLE (&bcm63xx_console)
|
|
#else
|
|
#define BCM63XX_CONSOLE NULL
|
|
#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
|
|
|
|
static struct uart_driver bcm_uart_driver = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "bcm63xx_uart",
|
|
.dev_name = "ttyS",
|
|
.major = TTY_MAJOR,
|
|
.minor = 64,
|
|
.nr = BCM63XX_NR_UARTS,
|
|
.cons = BCM63XX_CONSOLE,
|
|
};
|
|
|
|
/*
|
|
* platform driver probe/remove callback
|
|
*/
|
|
static int bcm_uart_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res_mem;
|
|
struct uart_port *port;
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
if (pdev->dev.of_node) {
|
|
pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
|
|
|
|
if (pdev->id < 0)
|
|
pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
|
|
}
|
|
|
|
if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
|
|
return -EINVAL;
|
|
|
|
port = &ports[pdev->id];
|
|
if (port->membase)
|
|
return -EBUSY;
|
|
memset(port, 0, sizeof(*port));
|
|
|
|
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res_mem)
|
|
return -ENODEV;
|
|
|
|
port->mapbase = res_mem->start;
|
|
port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
|
|
if (IS_ERR(port->membase))
|
|
return PTR_ERR(port->membase);
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
port->irq = ret;
|
|
|
|
clk = clk_get(&pdev->dev, "refclk");
|
|
if (IS_ERR(clk) && pdev->dev.of_node)
|
|
clk = of_clk_get(pdev->dev.of_node, 0);
|
|
|
|
if (IS_ERR(clk))
|
|
return -ENODEV;
|
|
|
|
port->iotype = UPIO_MEM;
|
|
port->ops = &bcm_uart_ops;
|
|
port->flags = UPF_BOOT_AUTOCONF;
|
|
port->dev = &pdev->dev;
|
|
port->fifosize = 16;
|
|
port->uartclk = clk_get_rate(clk) / 2;
|
|
port->line = pdev->id;
|
|
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
|
|
clk_put(clk);
|
|
|
|
ret = uart_add_one_port(&bcm_uart_driver, port);
|
|
if (ret) {
|
|
ports[pdev->id].membase = NULL;
|
|
return ret;
|
|
}
|
|
platform_set_drvdata(pdev, port);
|
|
return 0;
|
|
}
|
|
|
|
static int bcm_uart_remove(struct platform_device *pdev)
|
|
{
|
|
struct uart_port *port;
|
|
|
|
port = platform_get_drvdata(pdev);
|
|
uart_remove_one_port(&bcm_uart_driver, port);
|
|
/* mark port as free */
|
|
ports[pdev->id].membase = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id bcm63xx_of_match[] = {
|
|
{ .compatible = "brcm,bcm6345-uart" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
|
|
|
|
/*
|
|
* platform driver stuff
|
|
*/
|
|
static struct platform_driver bcm_uart_platform_driver = {
|
|
.probe = bcm_uart_probe,
|
|
.remove = bcm_uart_remove,
|
|
.driver = {
|
|
.name = "bcm63xx_uart",
|
|
.of_match_table = bcm63xx_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init bcm_uart_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = uart_register_driver(&bcm_uart_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&bcm_uart_platform_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&bcm_uart_driver);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit bcm_uart_exit(void)
|
|
{
|
|
platform_driver_unregister(&bcm_uart_platform_driver);
|
|
uart_unregister_driver(&bcm_uart_driver);
|
|
}
|
|
|
|
module_init(bcm_uart_init);
|
|
module_exit(bcm_uart_exit);
|
|
|
|
MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
|
|
MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
|
|
MODULE_LICENSE("GPL");
|