337 lines
8.3 KiB
C
337 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mtu3_dr.c - dual role switch and host glue layer
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*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include "mtu3.h"
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#include "mtu3_dr.h"
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/* mt8173 etc */
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#define PERI_WK_CTRL1 0x4
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#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
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#define WC1_IS_EN BIT(25)
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#define WC1_IS_P BIT(6) /* polarity for ip sleep */
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/* mt8183 */
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#define PERI_WK_CTRL0 0x0
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#define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
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#define WC0_IS_P BIT(12) /* polarity */
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#define WC0_IS_EN BIT(6)
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/* mt8192 */
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#define WC0_SSUSB0_CDEN BIT(6)
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#define WC0_IS_SPM_EN BIT(1)
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/* mt2712 etc */
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#define PERI_SSUSB_SPM_CTRL 0x0
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#define SSC_IP_SLEEP_EN BIT(4)
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#define SSC_SPM_INT_EN BIT(1)
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enum ssusb_uwk_vers {
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SSUSB_UWK_V1 = 1,
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SSUSB_UWK_V2,
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SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
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SSUSB_UWK_V1_2, /* specific revision 1.02 */
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};
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/*
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* ip-sleep wakeup mode:
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* all clocks can be turn off, but power domain should be kept on
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*/
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static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
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{
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u32 reg, msk, val;
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switch (ssusb->uwk_vers) {
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case SSUSB_UWK_V1:
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reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
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msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
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val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
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break;
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case SSUSB_UWK_V1_1:
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reg = ssusb->uwk_reg_base + PERI_WK_CTRL0;
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msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
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val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
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break;
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case SSUSB_UWK_V1_2:
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reg = ssusb->uwk_reg_base + PERI_WK_CTRL0;
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msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
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val = enable ? msk : 0;
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break;
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case SSUSB_UWK_V2:
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reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
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msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
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val = enable ? msk : 0;
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break;
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default:
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return;
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}
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regmap_update_bits(ssusb->uwk, reg, msk, val);
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}
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int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
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struct device_node *dn)
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{
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struct of_phandle_args args;
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int ret;
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/* wakeup function is optional */
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ssusb->uwk_en = of_property_read_bool(dn, "wakeup-source");
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if (!ssusb->uwk_en)
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return 0;
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ret = of_parse_phandle_with_fixed_args(dn,
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"mediatek,syscon-wakeup", 2, 0, &args);
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if (ret)
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return ret;
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ssusb->uwk_reg_base = args.args[0];
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ssusb->uwk_vers = args.args[1];
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ssusb->uwk = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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dev_info(ssusb->dev, "uwk - reg:0x%x, version:%d\n",
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ssusb->uwk_reg_base, ssusb->uwk_vers);
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return PTR_ERR_OR_ZERO(ssusb->uwk);
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}
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void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable)
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{
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if (ssusb->uwk_en)
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ssusb_wakeup_ip_sleep_set(ssusb, enable);
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}
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static void host_ports_num_get(struct ssusb_mtk *ssusb)
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{
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u32 xhci_cap;
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xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
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ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
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ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
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dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n",
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ssusb->u2_ports, ssusb->u3_ports);
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}
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/* only configure ports will be used later */
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static int ssusb_host_enable(struct ssusb_mtk *ssusb)
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{
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void __iomem *ibase = ssusb->ippc_base;
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int num_u3p = ssusb->u3_ports;
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int num_u2p = ssusb->u2_ports;
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int u3_ports_disabled;
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u32 check_clk;
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u32 value;
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int i;
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/* power on host ip */
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mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
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/* power on and enable u3 ports except skipped ones */
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u3_ports_disabled = 0;
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for (i = 0; i < num_u3p; i++) {
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if ((0x1 << i) & ssusb->u3p_dis_msk) {
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u3_ports_disabled++;
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continue;
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}
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value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
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value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
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value |= SSUSB_U3_PORT_HOST_SEL;
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mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
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}
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/* power on and enable all u2 ports */
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for (i = 0; i < num_u2p; i++) {
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if ((0x1 << i) & ssusb->u2p_dis_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
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value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
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value |= SSUSB_U2_PORT_HOST_SEL;
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mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
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}
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check_clk = SSUSB_XHCI_RST_B_STS;
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if (num_u3p > u3_ports_disabled)
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check_clk = SSUSB_U3_MAC_RST_B_STS;
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return ssusb_check_clocks(ssusb, check_clk);
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}
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static int ssusb_host_disable(struct ssusb_mtk *ssusb)
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{
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void __iomem *ibase = ssusb->ippc_base;
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int num_u3p = ssusb->u3_ports;
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int num_u2p = ssusb->u2_ports;
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u32 value;
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int i;
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/* power down and disable u3 ports except skipped ones */
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for (i = 0; i < num_u3p; i++) {
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if ((0x1 << i) & ssusb->u3p_dis_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
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value |= SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS;
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mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
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}
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/* power down and disable u2 ports except skipped ones */
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for (i = 0; i < num_u2p; i++) {
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if ((0x1 << i) & ssusb->u2p_dis_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
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value |= SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS;
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mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
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}
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/* power down host ip */
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mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
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return 0;
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}
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int ssusb_host_resume(struct ssusb_mtk *ssusb, bool p0_skipped)
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{
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void __iomem *ibase = ssusb->ippc_base;
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int u3p_skip_msk = ssusb->u3p_dis_msk;
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int u2p_skip_msk = ssusb->u2p_dis_msk;
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int num_u3p = ssusb->u3_ports;
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int num_u2p = ssusb->u2_ports;
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u32 value;
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int i;
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if (p0_skipped) {
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u2p_skip_msk |= 0x1;
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if (ssusb->otg_switch.is_u3_drd)
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u3p_skip_msk |= 0x1;
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}
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/* power on host ip */
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mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
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/* power on u3 ports except skipped ones */
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for (i = 0; i < num_u3p; i++) {
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if ((0x1 << i) & u3p_skip_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
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value &= ~SSUSB_U3_PORT_PDN;
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mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
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}
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/* power on all u2 ports except skipped ones */
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for (i = 0; i < num_u2p; i++) {
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if ((0x1 << i) & u2p_skip_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
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value &= ~SSUSB_U2_PORT_PDN;
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mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
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}
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return 0;
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}
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/* here not skip port0 due to PDN can be set repeatedly */
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int ssusb_host_suspend(struct ssusb_mtk *ssusb)
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{
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void __iomem *ibase = ssusb->ippc_base;
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int num_u3p = ssusb->u3_ports;
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int num_u2p = ssusb->u2_ports;
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u32 value;
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int i;
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/* power down u3 ports except skipped ones */
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for (i = 0; i < num_u3p; i++) {
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if ((0x1 << i) & ssusb->u3p_dis_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
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value |= SSUSB_U3_PORT_PDN;
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mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
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}
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/* power down u2 ports except skipped ones */
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for (i = 0; i < num_u2p; i++) {
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if ((0x1 << i) & ssusb->u2p_dis_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
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value |= SSUSB_U2_PORT_PDN;
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mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
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}
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/* power down host ip */
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mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
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return 0;
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}
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static void ssusb_host_setup(struct ssusb_mtk *ssusb)
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{
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host_ports_num_get(ssusb);
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/*
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* power on host and power on/enable all ports
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* if support OTG, gadget driver will switch port0 to device mode
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*/
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ssusb_host_enable(ssusb);
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ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
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/* if port0 supports dual-role, works as host mode by default */
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ssusb_set_vbus(&ssusb->otg_switch, 1);
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}
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static void ssusb_host_cleanup(struct ssusb_mtk *ssusb)
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{
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if (ssusb->is_host)
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ssusb_set_vbus(&ssusb->otg_switch, 0);
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ssusb_host_disable(ssusb);
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}
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/*
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* If host supports multiple ports, the VBUSes(5V) of ports except port0
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* which supports OTG are better to be enabled by default in DTS.
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* Because the host driver will keep link with devices attached when system
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* enters suspend mode, so no need to control VBUSes after initialization.
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*/
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int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn)
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{
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struct device *parent_dev = ssusb->dev;
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int ret;
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ssusb_host_setup(ssusb);
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ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev);
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if (ret) {
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dev_dbg(parent_dev, "failed to create child devices at %pOF\n",
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parent_dn);
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return ret;
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}
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dev_info(parent_dev, "xHCI platform device register success...\n");
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return 0;
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}
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void ssusb_host_exit(struct ssusb_mtk *ssusb)
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{
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of_platform_depopulate(ssusb->dev);
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ssusb_host_cleanup(ssusb);
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}
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