619 lines
15 KiB
C
619 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IMG I2S output controller driver
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*
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* Copyright (C) 2015 Imagination Technologies Ltd.
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*
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* Author: Damien Horsley <Damien.Horsley@imgtec.com>
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#define IMG_I2S_OUT_TX_FIFO 0x0
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#define IMG_I2S_OUT_CTL 0x4
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#define IMG_I2S_OUT_CTL_DATA_EN_MASK BIT(24)
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#define IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK 0xffe000
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#define IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT 13
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#define IMG_I2S_OUT_CTL_FRM_SIZE_MASK BIT(8)
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#define IMG_I2S_OUT_CTL_MASTER_MASK BIT(6)
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#define IMG_I2S_OUT_CTL_CLK_MASK BIT(5)
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#define IMG_I2S_OUT_CTL_CLK_EN_MASK BIT(4)
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#define IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK BIT(3)
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#define IMG_I2S_OUT_CTL_BCLK_POL_MASK BIT(2)
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#define IMG_I2S_OUT_CTL_ME_MASK BIT(0)
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#define IMG_I2S_OUT_CH_CTL 0x4
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#define IMG_I2S_OUT_CHAN_CTL_CH_MASK BIT(11)
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#define IMG_I2S_OUT_CHAN_CTL_LT_MASK BIT(10)
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#define IMG_I2S_OUT_CHAN_CTL_FMT_MASK 0xf0
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#define IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT 4
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#define IMG_I2S_OUT_CHAN_CTL_JUST_MASK BIT(3)
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#define IMG_I2S_OUT_CHAN_CTL_CLKT_MASK BIT(1)
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#define IMG_I2S_OUT_CHAN_CTL_ME_MASK BIT(0)
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#define IMG_I2S_OUT_CH_STRIDE 0x20
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struct img_i2s_out {
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void __iomem *base;
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struct clk *clk_sys;
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struct clk *clk_ref;
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struct snd_dmaengine_dai_dma_data dma_data;
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struct device *dev;
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unsigned int max_i2s_chan;
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void __iomem *channel_base;
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bool force_clk_active;
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unsigned int active_channels;
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struct reset_control *rst;
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struct snd_soc_dai_driver dai_driver;
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u32 suspend_ctl;
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u32 *suspend_ch_ctl;
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};
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static int img_i2s_out_runtime_suspend(struct device *dev)
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{
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struct img_i2s_out *i2s = dev_get_drvdata(dev);
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clk_disable_unprepare(i2s->clk_ref);
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clk_disable_unprepare(i2s->clk_sys);
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return 0;
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}
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static int img_i2s_out_runtime_resume(struct device *dev)
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{
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struct img_i2s_out *i2s = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(i2s->clk_sys);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(i2s->clk_ref);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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clk_disable_unprepare(i2s->clk_sys);
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return ret;
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}
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return 0;
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}
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static inline void img_i2s_out_writel(struct img_i2s_out *i2s, u32 val,
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u32 reg)
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{
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writel(val, i2s->base + reg);
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}
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static inline u32 img_i2s_out_readl(struct img_i2s_out *i2s, u32 reg)
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{
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return readl(i2s->base + reg);
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}
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static inline void img_i2s_out_ch_writel(struct img_i2s_out *i2s,
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u32 chan, u32 val, u32 reg)
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{
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writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
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}
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static inline u32 img_i2s_out_ch_readl(struct img_i2s_out *i2s, u32 chan,
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u32 reg)
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{
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return readl(i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
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}
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static inline void img_i2s_out_ch_disable(struct img_i2s_out *i2s, u32 chan)
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{
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u32 reg;
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reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
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reg &= ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
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img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
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}
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static inline void img_i2s_out_ch_enable(struct img_i2s_out *i2s, u32 chan)
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{
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u32 reg;
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reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
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reg |= IMG_I2S_OUT_CHAN_CTL_ME_MASK;
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img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
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}
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static inline void img_i2s_out_disable(struct img_i2s_out *i2s)
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{
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u32 reg;
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reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
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reg &= ~IMG_I2S_OUT_CTL_ME_MASK;
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img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
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}
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static inline void img_i2s_out_enable(struct img_i2s_out *i2s)
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{
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u32 reg;
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reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
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reg |= IMG_I2S_OUT_CTL_ME_MASK;
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img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
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}
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static void img_i2s_out_reset(struct img_i2s_out *i2s)
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{
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int i;
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u32 core_ctl, chan_ctl;
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core_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL) &
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~IMG_I2S_OUT_CTL_ME_MASK &
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~IMG_I2S_OUT_CTL_DATA_EN_MASK;
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if (!i2s->force_clk_active)
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core_ctl &= ~IMG_I2S_OUT_CTL_CLK_EN_MASK;
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chan_ctl = img_i2s_out_ch_readl(i2s, 0, IMG_I2S_OUT_CH_CTL) &
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~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
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reset_control_assert(i2s->rst);
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reset_control_deassert(i2s->rst);
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for (i = 0; i < i2s->max_i2s_chan; i++)
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img_i2s_out_ch_writel(i2s, i, chan_ctl, IMG_I2S_OUT_CH_CTL);
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_out_ch_enable(i2s, i);
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img_i2s_out_writel(i2s, core_ctl, IMG_I2S_OUT_CTL);
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img_i2s_out_enable(i2s);
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}
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static int img_i2s_out_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
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u32 reg;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
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if (!i2s->force_clk_active)
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reg |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
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reg |= IMG_I2S_OUT_CTL_DATA_EN_MASK;
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img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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img_i2s_out_reset(i2s);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int img_i2s_out_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned int channels, i2s_channels;
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long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
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int i;
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u32 reg, control_mask, control_set = 0;
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snd_pcm_format_t format;
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rate = params_rate(params);
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format = params_format(params);
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channels = params_channels(params);
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i2s_channels = channels / 2;
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if (format != SNDRV_PCM_FORMAT_S32_LE)
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return -EINVAL;
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if ((channels < 2) ||
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(channels > (i2s->max_i2s_chan * 2)) ||
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(channels % 2))
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return -EINVAL;
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pre_div_a = clk_round_rate(i2s->clk_ref, rate * 256);
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if (pre_div_a < 0)
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return pre_div_a;
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pre_div_b = clk_round_rate(i2s->clk_ref, rate * 384);
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if (pre_div_b < 0)
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return pre_div_b;
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diff_a = abs((pre_div_a / 256) - rate);
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diff_b = abs((pre_div_b / 384) - rate);
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/* If diffs are equal, use lower clock rate */
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if (diff_a > diff_b)
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clk_set_rate(i2s->clk_ref, pre_div_b);
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else
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clk_set_rate(i2s->clk_ref, pre_div_a);
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/*
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* Another driver (eg alsa machine driver) may have rejected the above
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* change. Get the current rate and set the register bit according to
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* the new minimum diff
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*/
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clk_rate = clk_get_rate(i2s->clk_ref);
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diff_a = abs((clk_rate / 256) - rate);
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diff_b = abs((clk_rate / 384) - rate);
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if (diff_a > diff_b)
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control_set |= IMG_I2S_OUT_CTL_CLK_MASK;
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control_set |= ((i2s_channels - 1) <<
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IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT) &
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IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
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control_mask = IMG_I2S_OUT_CTL_CLK_MASK |
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IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
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img_i2s_out_disable(i2s);
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reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
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reg = (reg & ~control_mask) | control_set;
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img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
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for (i = 0; i < i2s_channels; i++)
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img_i2s_out_ch_enable(i2s, i);
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for (; i < i2s->max_i2s_chan; i++)
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img_i2s_out_ch_disable(i2s, i);
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img_i2s_out_enable(i2s);
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i2s->active_channels = i2s_channels;
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return 0;
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}
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static int img_i2s_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
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int i, ret;
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bool force_clk_active;
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u32 chan_control_mask, control_mask, chan_control_set = 0;
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u32 reg, control_set = 0;
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force_clk_active = ((fmt & SND_SOC_DAIFMT_CLOCK_MASK) ==
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SND_SOC_DAIFMT_CONT);
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if (force_clk_active)
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control_set |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
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case SND_SOC_DAIFMT_BC_FC:
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break;
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case SND_SOC_DAIFMT_BP_FP:
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control_set |= IMG_I2S_OUT_CTL_MASTER_MASK;
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
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control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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break;
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case SND_SOC_DAIFMT_IB_IF:
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control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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chan_control_set |= IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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break;
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default:
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return -EINVAL;
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}
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control_mask = IMG_I2S_OUT_CTL_CLK_EN_MASK |
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IMG_I2S_OUT_CTL_MASTER_MASK |
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IMG_I2S_OUT_CTL_BCLK_POL_MASK |
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IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
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chan_control_mask = IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
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ret = pm_runtime_resume_and_get(i2s->dev);
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if (ret < 0)
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return ret;
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img_i2s_out_disable(i2s);
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reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
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reg = (reg & ~control_mask) | control_set;
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img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_out_ch_disable(i2s, i);
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for (i = 0; i < i2s->max_i2s_chan; i++) {
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reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
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reg = (reg & ~chan_control_mask) | chan_control_set;
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img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
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}
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_out_ch_enable(i2s, i);
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img_i2s_out_enable(i2s);
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pm_runtime_put(i2s->dev);
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i2s->force_clk_active = force_clk_active;
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return 0;
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}
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static const struct snd_soc_dai_ops img_i2s_out_dai_ops = {
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.trigger = img_i2s_out_trigger,
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.hw_params = img_i2s_out_hw_params,
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.set_fmt = img_i2s_out_set_fmt
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};
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static int img_i2s_out_dai_probe(struct snd_soc_dai *dai)
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{
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struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai, &i2s->dma_data, NULL);
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return 0;
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}
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static const struct snd_soc_component_driver img_i2s_out_component = {
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.name = "img-i2s-out",
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.legacy_dai_naming = 1,
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};
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static int img_i2s_out_dma_prepare_slave_config(struct snd_pcm_substream *st,
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struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
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{
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unsigned int i2s_channels = params_channels(params) / 2;
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struct snd_soc_pcm_runtime *rtd = st->private_data;
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struct snd_dmaengine_dai_dma_data *dma_data;
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int ret;
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dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
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ret = snd_hwparams_to_dma_slave_config(st, params, sc);
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if (ret)
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return ret;
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sc->dst_addr = dma_data->addr;
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sc->dst_addr_width = dma_data->addr_width;
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sc->dst_maxburst = 4 * i2s_channels;
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return 0;
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}
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static const struct snd_dmaengine_pcm_config img_i2s_out_dma_config = {
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.prepare_slave_config = img_i2s_out_dma_prepare_slave_config
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};
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static int img_i2s_out_probe(struct platform_device *pdev)
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{
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struct img_i2s_out *i2s;
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struct resource *res;
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void __iomem *base;
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int i, ret;
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unsigned int max_i2s_chan_pow_2;
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u32 reg;
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struct device *dev = &pdev->dev;
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i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
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if (!i2s)
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return -ENOMEM;
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platform_set_drvdata(pdev, i2s);
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i2s->dev = &pdev->dev;
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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i2s->base = base;
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|
|
if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
|
|
&i2s->max_i2s_chan)) {
|
|
dev_err(&pdev->dev, "No img,i2s-channels property\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
|
|
|
|
i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
|
|
|
|
i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
|
|
if (IS_ERR(i2s->rst))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->rst),
|
|
"No top level reset found\n");
|
|
|
|
i2s->clk_sys = devm_clk_get(&pdev->dev, "sys");
|
|
if (IS_ERR(i2s->clk_sys))
|
|
return dev_err_probe(dev, PTR_ERR(i2s->clk_sys),
|
|
"Failed to acquire clock 'sys'\n");
|
|
|
|
i2s->clk_ref = devm_clk_get(&pdev->dev, "ref");
|
|
if (IS_ERR(i2s->clk_ref))
|
|
return dev_err_probe(dev, PTR_ERR(i2s->clk_ref),
|
|
"Failed to acquire clock 'ref'\n");
|
|
|
|
i2s->suspend_ch_ctl = devm_kcalloc(dev,
|
|
i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
|
|
if (!i2s->suspend_ch_ctl)
|
|
return -ENOMEM;
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
ret = img_i2s_out_runtime_resume(&pdev->dev);
|
|
if (ret)
|
|
goto err_pm_disable;
|
|
}
|
|
ret = pm_runtime_resume_and_get(&pdev->dev);
|
|
if (ret < 0)
|
|
goto err_suspend;
|
|
|
|
reg = IMG_I2S_OUT_CTL_FRM_SIZE_MASK;
|
|
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
|
|
|
|
reg = IMG_I2S_OUT_CHAN_CTL_JUST_MASK |
|
|
IMG_I2S_OUT_CHAN_CTL_LT_MASK |
|
|
IMG_I2S_OUT_CHAN_CTL_CH_MASK |
|
|
(8 << IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT);
|
|
|
|
for (i = 0; i < i2s->max_i2s_chan; i++)
|
|
img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
|
|
|
|
img_i2s_out_reset(i2s);
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
i2s->active_channels = 1;
|
|
i2s->dma_data.addr = res->start + IMG_I2S_OUT_TX_FIFO;
|
|
i2s->dma_data.addr_width = 4;
|
|
i2s->dma_data.maxburst = 4;
|
|
|
|
i2s->dai_driver.probe = img_i2s_out_dai_probe;
|
|
i2s->dai_driver.playback.channels_min = 2;
|
|
i2s->dai_driver.playback.channels_max = i2s->max_i2s_chan * 2;
|
|
i2s->dai_driver.playback.rates = SNDRV_PCM_RATE_8000_192000;
|
|
i2s->dai_driver.playback.formats = SNDRV_PCM_FMTBIT_S32_LE;
|
|
i2s->dai_driver.ops = &img_i2s_out_dai_ops;
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev,
|
|
&img_i2s_out_component, &i2s->dai_driver, 1);
|
|
if (ret)
|
|
goto err_suspend;
|
|
|
|
ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
|
|
&img_i2s_out_dma_config, 0);
|
|
if (ret)
|
|
goto err_suspend;
|
|
|
|
return 0;
|
|
|
|
err_suspend:
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
img_i2s_out_runtime_suspend(&pdev->dev);
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int img_i2s_out_dev_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
img_i2s_out_runtime_suspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int img_i2s_out_suspend(struct device *dev)
|
|
{
|
|
struct img_i2s_out *i2s = dev_get_drvdata(dev);
|
|
int i, ret;
|
|
u32 reg;
|
|
|
|
if (pm_runtime_status_suspended(dev)) {
|
|
ret = img_i2s_out_runtime_resume(dev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < i2s->max_i2s_chan; i++) {
|
|
reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
|
|
i2s->suspend_ch_ctl[i] = reg;
|
|
}
|
|
|
|
i2s->suspend_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
|
|
|
|
img_i2s_out_runtime_suspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int img_i2s_out_resume(struct device *dev)
|
|
{
|
|
struct img_i2s_out *i2s = dev_get_drvdata(dev);
|
|
int i, ret;
|
|
u32 reg;
|
|
|
|
ret = img_i2s_out_runtime_resume(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < i2s->max_i2s_chan; i++) {
|
|
reg = i2s->suspend_ch_ctl[i];
|
|
img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
|
|
}
|
|
|
|
img_i2s_out_writel(i2s, i2s->suspend_ctl, IMG_I2S_OUT_CTL);
|
|
|
|
if (pm_runtime_status_suspended(dev))
|
|
img_i2s_out_runtime_suspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct of_device_id img_i2s_out_of_match[] = {
|
|
{ .compatible = "img,i2s-out" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, img_i2s_out_of_match);
|
|
|
|
static const struct dev_pm_ops img_i2s_out_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(img_i2s_out_runtime_suspend,
|
|
img_i2s_out_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(img_i2s_out_suspend, img_i2s_out_resume)
|
|
};
|
|
|
|
static struct platform_driver img_i2s_out_driver = {
|
|
.driver = {
|
|
.name = "img-i2s-out",
|
|
.of_match_table = img_i2s_out_of_match,
|
|
.pm = &img_i2s_out_pm_ops
|
|
},
|
|
.probe = img_i2s_out_probe,
|
|
.remove = img_i2s_out_dev_remove
|
|
};
|
|
module_platform_driver(img_i2s_out_driver);
|
|
|
|
MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
|
|
MODULE_DESCRIPTION("IMG I2S Output Driver");
|
|
MODULE_LICENSE("GPL v2");
|