123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_mvc.h - Definitions for Tegra210 MVC driver
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*
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* Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_MVC_H__
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#define __TEGRA210_MVC_H__
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/*
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* MVC_RX registers are with respect to XBAR.
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* The data comes from XBAR to MVC.
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*/
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#define TEGRA210_MVC_RX_STATUS 0x0c
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#define TEGRA210_MVC_RX_INT_STATUS 0x10
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#define TEGRA210_MVC_RX_INT_MASK 0x14
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#define TEGRA210_MVC_RX_INT_SET 0x18
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#define TEGRA210_MVC_RX_INT_CLEAR 0x1c
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#define TEGRA210_MVC_RX_CIF_CTRL 0x20
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/*
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* MVC_TX registers are with respect to XBAR.
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* The data goes out of MVC.
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*/
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#define TEGRA210_MVC_TX_STATUS 0x4c
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#define TEGRA210_MVC_TX_INT_STATUS 0x50
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#define TEGRA210_MVC_TX_INT_MASK 0x54
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#define TEGRA210_MVC_TX_INT_SET 0x58
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#define TEGRA210_MVC_TX_INT_CLEAR 0x5c
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#define TEGRA210_MVC_TX_CIF_CTRL 0x60
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/* Register offsets from TEGRA210_MVC*_BASE */
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#define TEGRA210_MVC_ENABLE 0x80
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#define TEGRA210_MVC_SOFT_RESET 0x84
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#define TEGRA210_MVC_CG 0x88
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#define TEGRA210_MVC_STATUS 0x90
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#define TEGRA210_MVC_INT_STATUS 0x94
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#define TEGRA210_MVC_CTRL 0xa8
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#define TEGRA210_MVC_SWITCH 0xac
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#define TEGRA210_MVC_INIT_VOL 0xb0
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#define TEGRA210_MVC_TARGET_VOL 0xd0
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#define TEGRA210_MVC_DURATION 0xf0
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#define TEGRA210_MVC_DURATION_INV 0xf4
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#define TEGRA210_MVC_POLY_N1 0xf8
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#define TEGRA210_MVC_POLY_N2 0xfc
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#define TEGRA210_MVC_PEAK_CTRL 0x100
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#define TEGRA210_MVC_CFG_RAM_CTRL 0x104
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#define TEGRA210_MVC_CFG_RAM_DATA 0x108
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#define TEGRA210_MVC_PEAK_VALUE 0x10c
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#define TEGRA210_MVC_CONFIG_ERR_TYPE 0x12c
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/* Fields in TEGRA210_MVC_ENABLE */
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#define TEGRA210_MVC_EN_SHIFT 0
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#define TEGRA210_MVC_EN (1 << TEGRA210_MVC_EN_SHIFT)
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#define TEGRA210_MVC_MUTE_SHIFT 8
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#define TEGRA210_MUTE_MASK_EN 0xff
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#define TEGRA210_MVC_MUTE_MASK (TEGRA210_MUTE_MASK_EN << TEGRA210_MVC_MUTE_SHIFT)
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#define TEGRA210_MVC_MUTE_EN (TEGRA210_MUTE_MASK_EN << TEGRA210_MVC_MUTE_SHIFT)
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#define TEGRA210_MVC_CH0_MUTE_EN 1
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#define TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT 30
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#define TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
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#define TEGRA210_MVC_PER_CHAN_CTRL_EN (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
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#define TEGRA210_MVC_CURVE_TYPE_SHIFT 1
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#define TEGRA210_MVC_CURVE_TYPE_MASK (1 << TEGRA210_MVC_CURVE_TYPE_SHIFT)
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#define TEGRA210_MVC_VOLUME_SWITCH_SHIFT 2
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#define TEGRA210_MVC_VOLUME_SWITCH_MASK (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
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#define TEGRA210_MVC_VOLUME_SWITCH_TRIGGER (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
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#define TEGRA210_MVC_CTRL_DEFAULT 0x40000003
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#define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY 0x01000000
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#define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR 0x00000000
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/* Fields in TEGRA210_MVC ram ctrl */
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#define TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT 14
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#define TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT)
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#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT 0
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#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_MASK (0x1ff << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT)
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#define REG_SIZE 4
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#define TEGRA210_MVC_MAX_CHAN_COUNT 8
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#define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i))
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#define TEGRA210_MVC_GET_CHAN(reg, base) (((reg) - (base)) / REG_SIZE)
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#define TEGRA210_GET_MUTE_VAL(val) (((val) >> TEGRA210_MVC_MUTE_SHIFT) & TEGRA210_MUTE_MASK_EN)
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#define NUM_GAIN_POLY_COEFFS 9
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enum {
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CURVE_POLY,
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CURVE_LINEAR,
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};
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struct tegra210_mvc_gain_params {
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int poly_coeff[NUM_GAIN_POLY_COEFFS];
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int poly_n1;
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int poly_n2;
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int duration;
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int duration_inv;
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};
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struct tegra210_mvc {
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int volume[TEGRA210_MVC_MAX_CHAN_COUNT];
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unsigned int curve_type;
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unsigned int ctrl_value;
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struct regmap *regmap;
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};
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#endif
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