83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ARM Generic Interrupt Controller (GIC) v3 specific defines
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*/
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#ifndef SELFTEST_KVM_GICV3_H
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#define SELFTEST_KVM_GICV3_H
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#include <asm/sysreg.h>
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/*
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* Distributor registers
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*/
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IGROUPR 0x0080
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#define GICD_ISENABLER 0x0100
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#define GICD_ICENABLER 0x0180
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#define GICD_ISPENDR 0x0200
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#define GICD_ICPENDR 0x0280
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#define GICD_ICACTIVER 0x0380
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#define GICD_ISACTIVER 0x0300
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#define GICD_IPRIORITYR 0x0400
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#define GICD_ICFGR 0x0C00
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/*
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* The assumption is that the guest runs in a non-secure mode.
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* The following bits of GICD_CTLR are defined accordingly.
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*/
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_nASSGIreq (1U << 8)
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#define GICD_CTLR_ARE_NS (1U << 4)
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#define GICD_CTLR_ENABLE_G1A (1U << 1)
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#define GICD_CTLR_ENABLE_G1 (1U << 0)
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#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
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#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0
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/*
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* Redistributor registers
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*/
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#define GICR_CTLR 0x000
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#define GICR_WAKER 0x014
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#define GICR_CTLR_RWP (1U << 3)
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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/*
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* Redistributor registers, offsets from SGI base
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*/
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#define GICR_IGROUPR0 GICD_IGROUPR
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#define GICR_ISENABLER0 GICD_ISENABLER
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#define GICR_ICENABLER0 GICD_ICENABLER
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#define GICR_ISPENDR0 GICD_ISPENDR
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#define GICR_ISACTIVER0 GICD_ISACTIVER
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#define GICR_ICACTIVER0 GICD_ICACTIVER
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#define GICR_ICENABLER GICD_ICENABLER
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#define GICR_ICACTIVER GICD_ICACTIVER
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#define GICR_IPRIORITYR0 GICD_IPRIORITYR
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/* CPU interface registers */
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#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
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#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
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#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
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#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
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#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
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#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
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#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
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#define SYS_ICV_AP1R0_EL1 sys_reg(3, 0, 12, 9, 0)
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#define ICC_PMR_DEF_PRIO 0xf0
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#define ICC_SRE_EL1_SRE (1U << 0)
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#define ICC_IGRPEN1_EL1_ENABLE (1U << 0)
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#define GICV3_MAX_CPUS 512
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#endif /* SELFTEST_KVM_GICV3_H */
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