303 lines
8.6 KiB
C
303 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ucna_injection_test
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*
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* Copyright (C) 2022, Google LLC.
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*
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* This work is licensed under the terms of the GNU GPL, version 2.
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*
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* Test that user space can inject UnCorrectable No Action required (UCNA)
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* memory errors to the guest.
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*
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* The test starts one vCPU with the MCG_CMCI_P enabled. It verifies that
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* proper UCNA errors can be injected to a vCPU with MCG_CMCI_P and
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* corresponding per-bank control register (MCI_CTL2) bit enabled.
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* The test also checks that the UCNA errors get recorded in the
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* Machine Check bank registers no matter the error signal interrupts get
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* delivered into the guest or not.
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*
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*/
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#define _GNU_SOURCE /* for program_invocation_short_name */
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#include <pthread.h>
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#include <inttypes.h>
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#include <string.h>
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#include <time.h>
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#include "kvm_util_base.h"
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#include "kvm_util.h"
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#include "mce.h"
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#include "processor.h"
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#include "test_util.h"
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#include "apic.h"
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#define SYNC_FIRST_UCNA 9
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#define SYNC_SECOND_UCNA 10
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#define SYNC_GP 11
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#define FIRST_UCNA_ADDR 0xdeadbeef
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#define SECOND_UCNA_ADDR 0xcafeb0ba
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/*
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* Vector for the CMCI interrupt.
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* Value is arbitrary. Any value in 0x20-0xFF should work:
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* https://wiki.osdev.org/Interrupt_Vector_Table
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*/
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#define CMCI_VECTOR 0xa9
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#define UCNA_BANK 0x7 // IMC0 bank
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#define MCI_CTL2_RESERVED_BIT BIT_ULL(29)
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static uint64_t supported_mcg_caps;
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/*
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* Record states about the injected UCNA.
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* The variables started with the 'i_' prefixes are recorded in interrupt
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* handler. Variables without the 'i_' prefixes are recorded in guest main
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* execution thread.
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*/
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static volatile uint64_t i_ucna_rcvd;
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static volatile uint64_t i_ucna_addr;
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static volatile uint64_t ucna_addr;
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static volatile uint64_t ucna_addr2;
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struct thread_params {
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struct kvm_vcpu *vcpu;
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uint64_t *p_i_ucna_rcvd;
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uint64_t *p_i_ucna_addr;
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uint64_t *p_ucna_addr;
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uint64_t *p_ucna_addr2;
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};
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static void verify_apic_base_addr(void)
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{
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uint64_t msr = rdmsr(MSR_IA32_APICBASE);
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uint64_t base = GET_APIC_BASE(msr);
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GUEST_ASSERT(base == APIC_DEFAULT_GPA);
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}
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static void ucna_injection_guest_code(void)
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{
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uint64_t ctl2;
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verify_apic_base_addr();
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xapic_enable();
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/* Sets up the interrupt vector and enables per-bank CMCI sigaling. */
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xapic_write_reg(APIC_LVTCMCI, CMCI_VECTOR | APIC_DM_FIXED);
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ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
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wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
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/* Enables interrupt in guest. */
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asm volatile("sti");
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/* Let user space inject the first UCNA */
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GUEST_SYNC(SYNC_FIRST_UCNA);
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ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
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/* Disables the per-bank CMCI signaling. */
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ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
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wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN);
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/* Let the user space inject the second UCNA */
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GUEST_SYNC(SYNC_SECOND_UCNA);
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ucna_addr2 = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
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GUEST_DONE();
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}
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static void cmci_disabled_guest_code(void)
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{
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uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
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wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
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GUEST_DONE();
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}
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static void cmci_enabled_guest_code(void)
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{
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uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
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wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT);
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GUEST_DONE();
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}
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static void guest_cmci_handler(struct ex_regs *regs)
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{
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i_ucna_rcvd++;
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i_ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
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xapic_write_reg(APIC_EOI, 0);
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}
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static void guest_gp_handler(struct ex_regs *regs)
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{
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GUEST_SYNC(SYNC_GP);
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}
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static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu)
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{
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struct ucall uc;
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vcpu_run(vcpu);
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TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
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TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_SYNC,
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"Expect UCALL_SYNC\n");
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TEST_ASSERT(uc.args[1] == SYNC_GP, "#GP is expected.");
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printf("vCPU received GP in guest.\n");
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}
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static void inject_ucna(struct kvm_vcpu *vcpu, uint64_t addr) {
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/*
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* A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in
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* the IA32_MCi_STATUS register.
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* MSCOD=1 (BIT[16] - MscodDataRdErr).
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* MCACOD=0x0090 (Memory controller error format, channel 0)
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*/
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uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
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MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090;
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struct kvm_x86_mce mce = {};
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mce.status = status;
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mce.mcg_status = 0;
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/*
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* MCM_ADDR_PHYS indicates the reported address is a physical address.
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* Lowest 6 bits is the recoverable address LSB, i.e., the injected MCE
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* is at 4KB granularity.
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*/
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mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
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mce.addr = addr;
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mce.bank = UCNA_BANK;
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vcpu_ioctl(vcpu, KVM_X86_SET_MCE, &mce);
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}
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static void *run_ucna_injection(void *arg)
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{
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struct thread_params *params = (struct thread_params *)arg;
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struct ucall uc;
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int old;
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int r;
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r = pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &old);
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TEST_ASSERT(r == 0,
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"pthread_setcanceltype failed with errno=%d",
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r);
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vcpu_run(params->vcpu);
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TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
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TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
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"Expect UCALL_SYNC\n");
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TEST_ASSERT(uc.args[1] == SYNC_FIRST_UCNA, "Injecting first UCNA.");
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printf("Injecting first UCNA at %#x.\n", FIRST_UCNA_ADDR);
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inject_ucna(params->vcpu, FIRST_UCNA_ADDR);
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vcpu_run(params->vcpu);
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TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
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TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
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"Expect UCALL_SYNC\n");
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TEST_ASSERT(uc.args[1] == SYNC_SECOND_UCNA, "Injecting second UCNA.");
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printf("Injecting second UCNA at %#x.\n", SECOND_UCNA_ADDR);
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inject_ucna(params->vcpu, SECOND_UCNA_ADDR);
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vcpu_run(params->vcpu);
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TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
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if (get_ucall(params->vcpu, &uc) == UCALL_ABORT) {
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TEST_ASSERT(false, "vCPU assertion failure: %s.\n",
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(const char *)uc.args[0]);
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}
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return NULL;
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}
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static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *params)
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{
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struct kvm_vm *vm = vcpu->vm;
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params->vcpu = vcpu;
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params->p_i_ucna_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_rcvd);
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params->p_i_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_addr);
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params->p_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr);
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params->p_ucna_addr2 = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr2);
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run_ucna_injection(params);
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TEST_ASSERT(*params->p_i_ucna_rcvd == 1, "Only first UCNA get signaled.");
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TEST_ASSERT(*params->p_i_ucna_addr == FIRST_UCNA_ADDR,
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"Only first UCNA reported addr get recorded via interrupt.");
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TEST_ASSERT(*params->p_ucna_addr == FIRST_UCNA_ADDR,
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"First injected UCNAs should get exposed via registers.");
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TEST_ASSERT(*params->p_ucna_addr2 == SECOND_UCNA_ADDR,
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"Second injected UCNAs should get exposed via registers.");
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printf("Test successful.\n"
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"UCNA CMCI interrupts received: %ld\n"
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"Last UCNA address received via CMCI: %lx\n"
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"First UCNA address in vCPU thread: %lx\n"
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"Second UCNA address in vCPU thread: %lx\n",
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*params->p_i_ucna_rcvd, *params->p_i_ucna_addr,
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*params->p_ucna_addr, *params->p_ucna_addr2);
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}
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static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p)
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{
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uint64_t mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS;
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if (enable_cmci_p)
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mcg_caps |= MCG_CMCI_P;
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mcg_caps &= supported_mcg_caps | MCG_CAP_BANKS_MASK;
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vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps);
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}
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static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, uint32_t vcpuid,
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bool enable_cmci_p, void *guest_code)
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{
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struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code);
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setup_mce_cap(vcpu, enable_cmci_p);
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return vcpu;
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}
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int main(int argc, char *argv[])
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{
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struct thread_params params;
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struct kvm_vm *vm;
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struct kvm_vcpu *ucna_vcpu;
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struct kvm_vcpu *cmcidis_vcpu;
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struct kvm_vcpu *cmci_vcpu;
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kvm_check_cap(KVM_CAP_MCE);
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vm = __vm_create(VM_MODE_DEFAULT, 3, 0);
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kvm_ioctl(vm->kvm_fd, KVM_X86_GET_MCE_CAP_SUPPORTED,
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&supported_mcg_caps);
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if (!(supported_mcg_caps & MCG_CMCI_P)) {
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print_skip("MCG_CMCI_P is not supported");
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exit(KSFT_SKIP);
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}
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ucna_vcpu = create_vcpu_with_mce_cap(vm, 0, true, ucna_injection_guest_code);
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cmcidis_vcpu = create_vcpu_with_mce_cap(vm, 1, false, cmci_disabled_guest_code);
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cmci_vcpu = create_vcpu_with_mce_cap(vm, 2, true, cmci_enabled_guest_code);
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vm_init_descriptor_tables(vm);
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vcpu_init_descriptor_tables(ucna_vcpu);
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vcpu_init_descriptor_tables(cmcidis_vcpu);
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vcpu_init_descriptor_tables(cmci_vcpu);
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vm_install_exception_handler(vm, CMCI_VECTOR, guest_cmci_handler);
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vm_install_exception_handler(vm, GP_VECTOR, guest_gp_handler);
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virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
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test_ucna_injection(ucna_vcpu, ¶ms);
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run_vcpu_expect_gp(cmcidis_vcpu);
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run_vcpu_expect_gp(cmci_vcpu);
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kvm_vm_free(vm);
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}
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