234 lines
7.4 KiB
C
234 lines
7.4 KiB
C
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* rseq-arm64.h
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*
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* (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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* (C) Copyright 2018 - Will Deacon <will.deacon@arm.com>
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*/
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/*
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* aarch64 -mbig-endian generates mixed endianness code vs data:
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* little-endian code and big-endian data. Ensure the RSEQ_SIG signature
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* matches code endianness.
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*/
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#define RSEQ_SIG_CODE 0xd428bc00 /* BRK #0x45E0. */
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#ifdef __AARCH64EB__
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#define RSEQ_SIG_DATA 0x00bc28d4 /* BRK #0x45E0. */
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#else
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#define RSEQ_SIG_DATA RSEQ_SIG_CODE
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#endif
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#define RSEQ_SIG RSEQ_SIG_DATA
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#define rseq_smp_mb() __asm__ __volatile__ ("dmb ish" ::: "memory")
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#define rseq_smp_rmb() __asm__ __volatile__ ("dmb ishld" ::: "memory")
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#define rseq_smp_wmb() __asm__ __volatile__ ("dmb ishst" ::: "memory")
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#define rseq_smp_load_acquire(p) \
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__extension__ ({ \
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__typeof(*p) ____p1; \
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switch (sizeof(*p)) { \
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case 1: \
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asm volatile ("ldarb %w0, %1" \
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: "=r" (*(__u8 *)p) \
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: "Q" (*p) : "memory"); \
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break; \
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case 2: \
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asm volatile ("ldarh %w0, %1" \
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: "=r" (*(__u16 *)p) \
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: "Q" (*p) : "memory"); \
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break; \
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case 4: \
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asm volatile ("ldar %w0, %1" \
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: "=r" (*(__u32 *)p) \
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: "Q" (*p) : "memory"); \
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break; \
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case 8: \
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asm volatile ("ldar %0, %1" \
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: "=r" (*(__u64 *)p) \
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: "Q" (*p) : "memory"); \
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break; \
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} \
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____p1; \
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})
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#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
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#define rseq_smp_store_release(p, v) \
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do { \
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switch (sizeof(*p)) { \
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case 1: \
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asm volatile ("stlrb %w1, %0" \
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: "=Q" (*p) \
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: "r" ((__u8)v) \
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: "memory"); \
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break; \
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case 2: \
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asm volatile ("stlrh %w1, %0" \
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: "=Q" (*p) \
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: "r" ((__u16)v) \
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: "memory"); \
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break; \
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case 4: \
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asm volatile ("stlr %w1, %0" \
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: "=Q" (*p) \
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: "r" ((__u32)v) \
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: "memory"); \
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break; \
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case 8: \
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asm volatile ("stlr %1, %0" \
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: "=Q" (*p) \
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: "r" ((__u64)v) \
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: "memory"); \
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break; \
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} \
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} while (0)
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#define RSEQ_ASM_TMP_REG32 "w15"
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#define RSEQ_ASM_TMP_REG "x15"
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#define RSEQ_ASM_TMP_REG_2 "x14"
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#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
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post_commit_offset, abort_ip) \
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" .pushsection __rseq_cs, \"aw\"\n" \
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" .balign 32\n" \
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__rseq_str(label) ":\n" \
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" .long " __rseq_str(version) ", " __rseq_str(flags) "\n" \
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" .quad " __rseq_str(start_ip) ", " \
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__rseq_str(post_commit_offset) ", " \
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__rseq_str(abort_ip) "\n" \
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" .popsection\n\t" \
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" .pushsection __rseq_cs_ptr_array, \"aw\"\n" \
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" .quad " __rseq_str(label) "b\n" \
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" .popsection\n"
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#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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/*
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* Exit points of a rseq critical section consist of all instructions outside
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* of the critical section where a critical section can either branch to or
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* reach through the normal course of its execution. The abort IP and the
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* post-commit IP are already part of the __rseq_cs section and should not be
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* explicitly defined as additional exit points. Knowing all exit points is
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* useful to assist debuggers stepping over the critical section.
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*/
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#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
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" .pushsection __rseq_exit_point_array, \"aw\"\n" \
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" .quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \
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" .popsection\n"
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#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
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RSEQ_INJECT_ASM(1) \
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" adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \
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" add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
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", :lo12:" __rseq_str(cs_label) "\n" \
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" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \
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__rseq_str(label) ":\n"
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#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \
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" b 222f\n" \
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" .inst " __rseq_str(RSEQ_SIG_CODE) "\n" \
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__rseq_str(label) ":\n" \
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" b %l[" __rseq_str(abort_label) "]\n" \
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"222:\n"
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#define RSEQ_ASM_OP_STORE(value, var) \
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" str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
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#define RSEQ_ASM_OP_STORE_RELEASE(value, var) \
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" stlr %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
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#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \
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RSEQ_ASM_OP_STORE(value, var) \
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__rseq_str(post_commit_label) ":\n"
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#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \
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RSEQ_ASM_OP_STORE_RELEASE(value, var) \
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__rseq_str(post_commit_label) ":\n"
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#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \
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" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
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" sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
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", %[" __rseq_str(expect) "]\n" \
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" cbnz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
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#define RSEQ_ASM_OP_CMPEQ32(var, expect, label) \
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" ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \
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" sub " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32 \
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", %w[" __rseq_str(expect) "]\n" \
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" cbnz " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"
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#define RSEQ_ASM_OP_CMPNE(var, expect, label) \
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" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
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" sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
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", %[" __rseq_str(expect) "]\n" \
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" cbz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
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#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
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RSEQ_INJECT_ASM(2) \
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RSEQ_ASM_OP_CMPEQ32(current_cpu_id, cpu_id, label)
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#define RSEQ_ASM_OP_R_LOAD(var) \
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" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
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#define RSEQ_ASM_OP_R_STORE(var) \
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" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
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#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \
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" ldr " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG \
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", %[" __rseq_str(offset) "]]\n"
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#define RSEQ_ASM_OP_R_ADD(count) \
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" add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
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", %[" __rseq_str(count) "]\n"
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#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
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" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
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__rseq_str(post_commit_label) ":\n"
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#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \
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" cbz %[" __rseq_str(len) "], 333f\n" \
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" mov " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n" \
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"222: sub " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n" \
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" ldrb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]" \
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", " RSEQ_ASM_TMP_REG_2 "]\n" \
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" strb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]" \
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", " RSEQ_ASM_TMP_REG_2 "]\n" \
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" cbnz " RSEQ_ASM_TMP_REG_2 ", 222b\n" \
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"333:\n"
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/* Per-cpu-id indexing. */
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#define RSEQ_TEMPLATE_CPU_ID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-arm64-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-arm64-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_CPU_ID
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/* Per-mm-cid indexing. */
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#define RSEQ_TEMPLATE_MM_CID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-arm64-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-arm64-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_MM_CID
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/* APIs which are not based on cpu ids. */
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#define RSEQ_TEMPLATE_CPU_ID_NONE
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-arm64-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#undef RSEQ_TEMPLATE_CPU_ID_NONE
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