182 lines
5.4 KiB
C
182 lines
5.4 KiB
C
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* Author: Paul Burton <paul.burton@mips.com>
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* (C) Copyright 2018 MIPS Tech LLC
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* (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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*/
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/*
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* RSEQ_SIG uses the break instruction. The instruction pattern is:
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*
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* On MIPS:
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* 0350000d break 0x350
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*
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* On nanoMIPS:
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* 00100350 break 0x350
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*
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* On microMIPS:
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* 0000d407 break 0x350
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*
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* For nanoMIPS32 and microMIPS, the instruction stream is encoded as 16-bit
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* halfwords, so the signature halfwords need to be swapped accordingly for
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* little-endian.
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*/
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#if defined(__nanomips__)
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# ifdef __MIPSEL__
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# define RSEQ_SIG 0x03500010
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# else
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# define RSEQ_SIG 0x00100350
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# endif
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#elif defined(__mips_micromips)
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# ifdef __MIPSEL__
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# define RSEQ_SIG 0xd4070000
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# else
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# define RSEQ_SIG 0x0000d407
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# endif
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#elif defined(__mips__)
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# define RSEQ_SIG 0x0350000d
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#else
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/* Unknown MIPS architecture. */
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#endif
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#define rseq_smp_mb() __asm__ __volatile__ ("sync" ::: "memory")
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#define rseq_smp_rmb() rseq_smp_mb()
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#define rseq_smp_wmb() rseq_smp_mb()
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#define rseq_smp_load_acquire(p) \
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__extension__ ({ \
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__typeof(*p) ____p1 = RSEQ_READ_ONCE(*p); \
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rseq_smp_mb(); \
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____p1; \
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})
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#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
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#define rseq_smp_store_release(p, v) \
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do { \
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rseq_smp_mb(); \
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RSEQ_WRITE_ONCE(*p, v); \
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} while (0)
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#if _MIPS_SZLONG == 64
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# define LONG ".dword"
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# define LONG_LA "dla"
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# define LONG_L "ld"
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# define LONG_S "sd"
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# define LONG_ADDI "daddiu"
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# define U32_U64_PAD(x) x
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#elif _MIPS_SZLONG == 32
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# define LONG ".word"
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# define LONG_LA "la"
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# define LONG_L "lw"
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# define LONG_S "sw"
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# define LONG_ADDI "addiu"
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# ifdef __BIG_ENDIAN
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# define U32_U64_PAD(x) "0x0, " x
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# else
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# define U32_U64_PAD(x) x ", 0x0"
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# endif
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#else
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# error unsupported _MIPS_SZLONG
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#endif
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#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
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post_commit_offset, abort_ip) \
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".pushsection __rseq_cs, \"aw\"\n\t" \
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".balign 32\n\t" \
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__rseq_str(label) ":\n\t" \
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".word " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(start_ip)) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(post_commit_offset)) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(abort_ip)) "\n\t" \
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".popsection\n\t" \
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".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(label) "b") "\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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/*
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* Exit points of a rseq critical section consist of all instructions outside
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* of the critical section where a critical section can either branch to or
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* reach through the normal course of its execution. The abort IP and the
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* post-commit IP are already part of the __rseq_cs section and should not be
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* explicitly defined as additional exit points. Knowing all exit points is
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* useful to assist debuggers stepping over the critical section.
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*/
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#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
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".pushsection __rseq_exit_point_array, \"aw\"\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(start_ip)) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(exit_ip)) "\n\t" \
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".popsection\n\t"
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#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
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RSEQ_INJECT_ASM(1) \
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LONG_LA " $4, " __rseq_str(cs_label) "\n\t" \
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LONG_S " $4, %[" __rseq_str(rseq_cs) "]\n\t" \
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__rseq_str(label) ":\n\t"
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#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
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RSEQ_INJECT_ASM(2) \
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"lw $4, %[" __rseq_str(current_cpu_id) "]\n\t" \
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"bne $4, %[" __rseq_str(cpu_id) "], " __rseq_str(label) "\n\t"
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#define __RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, \
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abort_label, version, flags, \
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start_ip, post_commit_offset, abort_ip) \
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".balign 32\n\t" \
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__rseq_str(table_label) ":\n\t" \
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".word " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(start_ip)) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(post_commit_offset)) "\n\t" \
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LONG " " U32_U64_PAD(__rseq_str(abort_ip)) "\n\t" \
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".word " __rseq_str(RSEQ_SIG) "\n\t" \
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__rseq_str(label) ":\n\t" \
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teardown \
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"b %l[" __rseq_str(abort_label) "]\n\t"
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#define RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, abort_label, \
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start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_ABORT(table_label, label, teardown, \
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abort_label, 0x0, 0x0, start_ip, \
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(post_commit_ip - start_ip), abort_ip)
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#define RSEQ_ASM_DEFINE_CMPFAIL(label, teardown, cmpfail_label) \
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__rseq_str(label) ":\n\t" \
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teardown \
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"b %l[" __rseq_str(cmpfail_label) "]\n\t"
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/* Per-cpu-id indexing. */
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#define RSEQ_TEMPLATE_CPU_ID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-mips-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-mips-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_CPU_ID
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/* Per-mm-cid indexing. */
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#define RSEQ_TEMPLATE_MM_CID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-mips-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-mips-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_MM_CID
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/* APIs which are not based on cpu ids. */
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#define RSEQ_TEMPLATE_CPU_ID_NONE
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-mips-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#undef RSEQ_TEMPLATE_CPU_ID_NONE
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