715 lines
17 KiB
Plaintext
715 lines
17 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for AM33XX SoC
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/am33xx.h>
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#include <dt-bindings/clock/am3.h>
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/ {
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compatible = "ti,am33xx";
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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d-can0 = &dcan0;
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d-can1 = &dcan1;
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usb0 = &usb0;
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usb1 = &usb1;
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phy0 = &usb0_phy;
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phy1 = &usb1_phy;
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ethernet0 = &cpsw_port1;
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ethernet1 = &cpsw_port2;
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spi0 = &spi0;
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spi1 = &spi1;
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mmc0 = &mmc1;
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mmc1 = &mmc2;
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mmc2 = &mmc3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a8";
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enable-method = "ti,am3352";
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device_type = "cpu";
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reg = <0>;
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operating-points-v2 = <&cpu0_opp_table>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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cpu-idle-states = <&mpu_gate>;
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};
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idle-states {
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mpu_gate: mpu_gate {
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compatible = "arm,idle-state";
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entry-latency-us = <40>;
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exit-latency-us = <90>;
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min-residency-us = <300>;
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ti,idle-wkup-m3;
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};
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};
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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/*
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* The three following nodes are marked with opp-suspend
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* because the can not be enabled simultaneously on a
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* single SoC.
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*/
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opp50-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <950000 931000 969000>;
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opp-supported-hw = <0x06 0x0010>;
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opp-suspend;
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};
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opp100-275000000 {
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opp-hz = /bits/ 64 <275000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x01 0x00FF>;
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opp-suspend;
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};
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opp100-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x06 0x0020>;
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opp-suspend;
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};
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opp100-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x01 0xFFFF>;
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};
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opp100-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x06 0x0040>;
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};
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opp120-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0x01 0xFFFF>;
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};
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opp120-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0x06 0x0080>;
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};
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oppturbo-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0x01 0xFFFF>;
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};
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oppturbo-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0x06 0x0100>;
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};
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oppnitro-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1325000 1298500 1351500>;
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opp-supported-hw = <0x04 0x0200>;
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};
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};
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target-module@4b000000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4b000000 0x1000000>;
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target-module@140000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x140000 0xec0000>;
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pmu@0 {
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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};
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};
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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};
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/*
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* XXX: Use a flat representation of the AM33XX interconnect.
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* The real AM33XX interconnect network is quite complex. Since
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* it will not bring real advantage to represent that in DT
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* for the moment, just use a fake OCP bus entry to represent
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* the whole bus hierarchy.
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*/
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ocp: ocp {
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compatible = "simple-pm-bus";
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power-domains = <&prm_per>;
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clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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l4_wkup: interconnect@44c00000 {
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};
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l4_per: interconnect@48000000 {
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};
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l4_fw: interconnect@47c00000 {
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};
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l4_fast: interconnect@4a000000 {
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};
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l4_mpuss: interconnect@4b140000 {
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};
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intc: interrupt-controller@48200000 {
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compatible = "ti,am33xx-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x48200000 0x1000>;
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};
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target-module@49000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49000000 0x4>;
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reg-names = "rev";
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clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49000000 0x10000>;
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edma: dma@0 {
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compatible = "ti,edma3-tpcc";
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reg = <0 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <20 21>;
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};
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};
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target-module@49800000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49800000 0x4>,
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<0x49800010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49800000 0x100000>;
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edma_tptc0: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <112>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49900000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49900000 0x4>,
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<0x49900010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49900000 0x100000>;
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edma_tptc1: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <113>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49a00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49a00000 0x4>,
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<0x49a00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49a00000 0x100000>;
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edma_tptc2: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <114>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@47810000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x478102fc 0x4>,
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<0x47810110 0x4>,
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<0x47810114 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x47810000 0x1000>;
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mmc3: mmc@0 {
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compatible = "ti,am335-sdhci";
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ti,needs-special-reset;
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interrupts = <29>;
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reg = <0x0 0x1000>;
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status = "disabled";
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};
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};
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usb: target-module@47400000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x47400000 0x4>,
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<0x47400010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
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SYSC_OMAP4_SOFTRESET)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x47400000 0x8000>;
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usb0_phy: usb-phy@1300 {
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compatible = "ti,am335x-usb-phy";
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reg = <0x1300 0x100>;
|
||
|
|
reg-names = "phy";
|
||
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb0: usb@1400 {
|
||
|
|
compatible = "ti,musb-am33xx";
|
||
|
|
reg = <0x1400 0x400>,
|
||
|
|
<0x1000 0x200>;
|
||
|
|
reg-names = "mc", "control";
|
||
|
|
|
||
|
|
interrupts = <18>;
|
||
|
|
interrupt-names = "mc";
|
||
|
|
dr_mode = "otg";
|
||
|
|
mentor,multipoint = <1>;
|
||
|
|
mentor,num-eps = <16>;
|
||
|
|
mentor,ram-bits = <12>;
|
||
|
|
mentor,power = <500>;
|
||
|
|
phys = <&usb0_phy>;
|
||
|
|
|
||
|
|
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
||
|
|
&cppi41dma 2 0 &cppi41dma 3 0
|
||
|
|
&cppi41dma 4 0 &cppi41dma 5 0
|
||
|
|
&cppi41dma 6 0 &cppi41dma 7 0
|
||
|
|
&cppi41dma 8 0 &cppi41dma 9 0
|
||
|
|
&cppi41dma 10 0 &cppi41dma 11 0
|
||
|
|
&cppi41dma 12 0 &cppi41dma 13 0
|
||
|
|
&cppi41dma 14 0 &cppi41dma 0 1
|
||
|
|
&cppi41dma 1 1 &cppi41dma 2 1
|
||
|
|
&cppi41dma 3 1 &cppi41dma 4 1
|
||
|
|
&cppi41dma 5 1 &cppi41dma 6 1
|
||
|
|
&cppi41dma 7 1 &cppi41dma 8 1
|
||
|
|
&cppi41dma 9 1 &cppi41dma 10 1
|
||
|
|
&cppi41dma 11 1 &cppi41dma 12 1
|
||
|
|
&cppi41dma 13 1 &cppi41dma 14 1>;
|
||
|
|
dma-names =
|
||
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
||
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
||
|
|
"rx14", "rx15",
|
||
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
||
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
||
|
|
"tx14", "tx15";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb1_phy: usb-phy@1b00 {
|
||
|
|
compatible = "ti,am335x-usb-phy";
|
||
|
|
reg = <0x1b00 0x100>;
|
||
|
|
reg-names = "phy";
|
||
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb1: usb@1800 {
|
||
|
|
compatible = "ti,musb-am33xx";
|
||
|
|
reg = <0x1c00 0x400>,
|
||
|
|
<0x1800 0x200>;
|
||
|
|
reg-names = "mc", "control";
|
||
|
|
interrupts = <19>;
|
||
|
|
interrupt-names = "mc";
|
||
|
|
dr_mode = "otg";
|
||
|
|
mentor,multipoint = <1>;
|
||
|
|
mentor,num-eps = <16>;
|
||
|
|
mentor,ram-bits = <12>;
|
||
|
|
mentor,power = <500>;
|
||
|
|
phys = <&usb1_phy>;
|
||
|
|
|
||
|
|
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
||
|
|
&cppi41dma 17 0 &cppi41dma 18 0
|
||
|
|
&cppi41dma 19 0 &cppi41dma 20 0
|
||
|
|
&cppi41dma 21 0 &cppi41dma 22 0
|
||
|
|
&cppi41dma 23 0 &cppi41dma 24 0
|
||
|
|
&cppi41dma 25 0 &cppi41dma 26 0
|
||
|
|
&cppi41dma 27 0 &cppi41dma 28 0
|
||
|
|
&cppi41dma 29 0 &cppi41dma 15 1
|
||
|
|
&cppi41dma 16 1 &cppi41dma 17 1
|
||
|
|
&cppi41dma 18 1 &cppi41dma 19 1
|
||
|
|
&cppi41dma 20 1 &cppi41dma 21 1
|
||
|
|
&cppi41dma 22 1 &cppi41dma 23 1
|
||
|
|
&cppi41dma 24 1 &cppi41dma 25 1
|
||
|
|
&cppi41dma 26 1 &cppi41dma 27 1
|
||
|
|
&cppi41dma 28 1 &cppi41dma 29 1>;
|
||
|
|
dma-names =
|
||
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
||
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
||
|
|
"rx14", "rx15",
|
||
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
||
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
||
|
|
"tx14", "tx15";
|
||
|
|
};
|
||
|
|
|
||
|
|
cppi41dma: dma-controller@2000 {
|
||
|
|
compatible = "ti,am3359-cppi41";
|
||
|
|
reg = <0x0000 0x1000>,
|
||
|
|
<0x2000 0x1000>,
|
||
|
|
<0x3000 0x1000>,
|
||
|
|
<0x4000 0x4000>;
|
||
|
|
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
||
|
|
interrupts = <17>;
|
||
|
|
interrupt-names = "glue";
|
||
|
|
#dma-cells = <2>;
|
||
|
|
/* For backwards compatibility: */
|
||
|
|
#dma-channels = <30>;
|
||
|
|
dma-channels = <30>;
|
||
|
|
#dma-requests = <256>;
|
||
|
|
dma-requests = <256>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
target-module@40300000 {
|
||
|
|
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||
|
|
clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
|
||
|
|
clock-names = "fck";
|
||
|
|
ti,no-idle;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x40300000 0x10000>;
|
||
|
|
|
||
|
|
ocmcram: sram@0 {
|
||
|
|
compatible = "mmio-sram";
|
||
|
|
reg = <0 0x10000>; /* 64k */
|
||
|
|
ranges = <0 0 0x10000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
pm_sram_code: pm-code-sram@0 {
|
||
|
|
compatible = "ti,sram";
|
||
|
|
reg = <0x0 0x1000>;
|
||
|
|
protect-exec;
|
||
|
|
};
|
||
|
|
|
||
|
|
pm_sram_data: pm-data-sram@1000 {
|
||
|
|
compatible = "ti,sram";
|
||
|
|
reg = <0x1000 0x1000>;
|
||
|
|
pool;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
target-module@4c000000 {
|
||
|
|
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||
|
|
reg = <0x4c000000 0x4>;
|
||
|
|
reg-names = "rev";
|
||
|
|
clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
|
||
|
|
clock-names = "fck";
|
||
|
|
ti,no-idle;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0x0 0x4c000000 0x1000000>;
|
||
|
|
|
||
|
|
emif: emif@0 {
|
||
|
|
compatible = "ti,emif-am3352";
|
||
|
|
reg = <0 0x1000000>;
|
||
|
|
interrupts = <101>;
|
||
|
|
sram = <&pm_sram_code
|
||
|
|
&pm_sram_data>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
target-module@50000000 {
|
||
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
||
|
|
reg = <0x50000000 4>,
|
||
|
|
<0x50000010 4>,
|
||
|
|
<0x50000014 4>;
|
||
|
|
reg-names = "rev", "sysc", "syss";
|
||
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||
|
|
<SYSC_IDLE_NO>,
|
||
|
|
<SYSC_IDLE_SMART>;
|
||
|
|
ti,syss-mask = <1>;
|
||
|
|
clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
|
||
|
|
clock-names = "fck";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
|
||
|
|
<0x00000000 0x00000000 0x40000000>; /* data */
|
||
|
|
|
||
|
|
gpmc: gpmc@50000000 {
|
||
|
|
compatible = "ti,am3352-gpmc";
|
||
|
|
reg = <0x50000000 0x2000>;
|
||
|
|
interrupts = <100>;
|
||
|
|
dmas = <&edma 52 0>;
|
||
|
|
dma-names = "rxtx";
|
||
|
|
gpmc,num-cs = <7>;
|
||
|
|
gpmc,num-waitpins = <2>;
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sham_target: target-module@53100000 {
|
||
|
|
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
||
|
|
reg = <0x53100100 0x4>,
|
||
|
|
<0x53100110 0x4>,
|
||
|
|
<0x53100114 0x4>;
|
||
|
|
reg-names = "rev", "sysc", "syss";
|
||
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
||
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||
|
|
<SYSC_IDLE_NO>,
|
||
|
|
<SYSC_IDLE_SMART>;
|
||
|
|
ti,syss-mask = <1>;
|
||
|
|
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
||
|
|
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
|
||
|
|
clock-names = "fck";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0x0 0x53100000 0x1000>;
|
||
|
|
|
||
|
|
sham: sham@0 {
|
||
|
|
compatible = "ti,omap4-sham";
|
||
|
|
reg = <0 0x200>;
|
||
|
|
interrupts = <109>;
|
||
|
|
dmas = <&edma 36 0>;
|
||
|
|
dma-names = "rx";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
aes_target: target-module@53500000 {
|
||
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
||
|
|
reg = <0x53500080 0x4>,
|
||
|
|
<0x53500084 0x4>,
|
||
|
|
<0x53500088 0x4>;
|
||
|
|
reg-names = "rev", "sysc", "syss";
|
||
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
||
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||
|
|
<SYSC_IDLE_NO>,
|
||
|
|
<SYSC_IDLE_SMART>,
|
||
|
|
<SYSC_IDLE_SMART_WKUP>;
|
||
|
|
ti,syss-mask = <1>;
|
||
|
|
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
||
|
|
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
|
||
|
|
clock-names = "fck";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0x0 0x53500000 0x1000>;
|
||
|
|
|
||
|
|
aes: aes@0 {
|
||
|
|
compatible = "ti,omap4-aes";
|
||
|
|
reg = <0 0xa0>;
|
||
|
|
interrupts = <103>;
|
||
|
|
dmas = <&edma 6 0>,
|
||
|
|
<&edma 5 0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
target-module@56000000 {
|
||
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
||
|
|
reg = <0x5600fe00 0x4>,
|
||
|
|
<0x5600fe10 0x4>;
|
||
|
|
reg-names = "rev", "sysc";
|
||
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||
|
|
<SYSC_IDLE_NO>,
|
||
|
|
<SYSC_IDLE_SMART>;
|
||
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||
|
|
<SYSC_IDLE_NO>,
|
||
|
|
<SYSC_IDLE_SMART>;
|
||
|
|
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
|
||
|
|
clock-names = "fck";
|
||
|
|
power-domains = <&prm_gfx>;
|
||
|
|
resets = <&prm_gfx 0>;
|
||
|
|
reset-names = "rstctrl";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x56000000 0x1000000>;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Closed source PowerVR driver, no child device
|
||
|
|
* binding or driver in mainline
|
||
|
|
*/
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "am33xx-l4.dtsi"
|
||
|
|
#include "am33xx-clocks.dtsi"
|
||
|
|
|
||
|
|
&prcm {
|
||
|
|
prm_per: prm@c00 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0xc00 0x100>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
prm_wkup: prm@d00 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0xd00 0x100>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
prm_mpu: prm@e00 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0xe00 0x100>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
prm_device: prm@f00 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0xf00 0x100>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
prm_rtc: prm@1000 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0x1000 0x100>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
prm_gfx: prm@1100 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0x1100 0x100>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
prm_cefuse: prm@1200 {
|
||
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||
|
|
reg = <0x1200 0x100>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Preferred always-on timer for clocksource */
|
||
|
|
&timer1_target {
|
||
|
|
clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
|
||
|
|
<&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
|
||
|
|
clock-names = "fck", "ick";
|
||
|
|
ti,no-reset-on-init;
|
||
|
|
ti,no-idle;
|
||
|
|
timer@0 {
|
||
|
|
assigned-clocks = <&timer1_fck>;
|
||
|
|
assigned-clock-parents = <&sys_clkin_ck>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Preferred timer for clockevent */
|
||
|
|
&timer2_target {
|
||
|
|
clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
|
||
|
|
<&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
|
||
|
|
clock-names = "fck", "ick";
|
||
|
|
ti,no-reset-on-init;
|
||
|
|
ti,no-idle;
|
||
|
|
timer@0 {
|
||
|
|
assigned-clocks = <&timer2_fck>;
|
||
|
|
assigned-clock-parents = <&sys_clkin_ck>;
|
||
|
|
};
|
||
|
|
};
|