143 lines
2.6 KiB
Plaintext
143 lines
2.6 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell RD-AXPWiFiAP.
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*
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* Note: this board is shipped with a new generation boot loader that
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* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
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* is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
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* CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
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*
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* Copyright (C) 2013 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "armada-xp-mv78230.dtsi"
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/ {
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model = "Marvell RD-AXPWiFiAP";
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compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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internal-regs {
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/* UART0 */
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serial@12000 {
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status = "okay";
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};
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/* UART1 */
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serial@12100 {
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status = "okay";
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};
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sata@a0000 {
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nr-ports = <1>;
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status = "okay";
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};
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ethernet@70000 {
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@74000 {
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pinctrl-0 = <&ge1_rgmii_pins>;
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pinctrl-names = "default";
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&keys_pin>;
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pinctrl-names = "default";
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button-reset {
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label = "Factory Reset Button";
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linux,code = <KEY_SETUP>;
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gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&pciec {
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status = "okay";
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/* First mini-PCIe port */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Second mini-PCIe port */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Renesas uPD720202 USB 3.0 controller */
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pcie@3,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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};
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&pinctrl {
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pinctrl-0 = <&phy_int_pin>;
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pinctrl-names = "default";
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keys_pin: keys-pin {
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marvell,pins = "mpp33";
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marvell,function = "gpio";
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};
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phy_int_pin: phy-int-pin {
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marvell,pins = "mpp32";
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marvell,function = "gpio";
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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