111 lines
2.1 KiB
Plaintext
111 lines
2.1 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
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*
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* Based on "omap4.dtsi"
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*/
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#include "dra7.dtsi"
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/ {
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compatible = "ti,dra722", "ti,dra72", "ti,dra7";
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aliases {
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rproc0 = &ipu1;
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rproc1 = &ipu2;
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rproc2 = &dsp1;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupt-parent = <&wakeupgen>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&l4_per2 {
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target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5b000 0x4>,
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<0x5b010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x5b000 0x1000>;
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cal: cal@0 {
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compatible = "ti,dra72-cal";
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reg = <0x0000 0x400>,
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<0x0800 0x40>,
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<0x0900 0x40>;
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reg-names = "cal_top",
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"cal_rx_core0",
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"cal_rx_core1";
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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ti,camerrx-control = <&scm_conf 0xE94>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi2_0: port@0 {
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reg = <0>;
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};
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csi2_1: port@1 {
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reg = <1>;
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};
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};
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};
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};
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};
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&dss {
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reg = <0 0x80>,
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<0x4054 0x4>,
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<0x4300 0x20>;
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reg-names = "dss", "pll1_clkctrl", "pll1";
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clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
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<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
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clock-names = "fck", "video1_clk";
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};
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&mailbox5 {
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mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
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ti,mbox-tx = <6 2 2>;
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ti,mbox-rx = <4 2 2>;
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status = "disabled";
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};
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mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
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ti,mbox-tx = <5 2 2>;
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ti,mbox-rx = <1 2 2>;
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status = "disabled";
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};
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};
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&mailbox6 {
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mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
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ti,mbox-tx = <6 2 2>;
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ti,mbox-rx = <4 2 2>;
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status = "disabled";
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};
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};
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&pcie1_rc {
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compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
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};
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&pcie1_ep {
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compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
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};
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&pcie2_rc {
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compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
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};
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