106 lines
2.4 KiB
Plaintext
106 lines
2.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HiSilicon Ltd. HiP01 SoC
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*
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* Copyright (c) 2014 HiSilicon Ltd.
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* Copyright (c) 2014 Huawei Ltd.
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*
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* Author: Wang Long <long.wanglong@huawei.com>
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*/
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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gic: interrupt-controller@1e001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
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};
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hisi_refclk144mhz: refclk144mkhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <144000000>;
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clock-output-names = "hisi:refclk144khz";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0 0x10000000 0x20000000>;
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amba-bus {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: serial@10001000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10001000 0x1000>;
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 32 4>;
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status = "disabled";
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};
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uart1: serial@10002000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10002000 0x1000>;
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 33 4>;
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status = "disabled";
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};
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uart2: serial@10003000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10003000 0x1000>;
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 34 4>;
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status = "disabled";
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};
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uart3: serial@10006000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10006000 0x1000>;
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 4 4>;
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status = "disabled";
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};
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};
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system-controller@10000000 {
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compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
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reg = <0x10000000 0x1000>;
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reboot-offset = <0x4>;
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};
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global_timer@a000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x0a000200 0x100>;
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interrupts = <1 11 0xf04>;
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clocks = <&hisi_refclk144mhz>;
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};
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local_timer@a000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x0a000600 0x100>;
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interrupts = <1 13 0xf04>;
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clocks = <&hisi_refclk144mhz>;
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};
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};
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};
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